This project implements a custom 32-bit RISC processor, inspired by the MIPS architecture. It was developed as part of the Computer Organization Laboratory course under the guidance of Prof. Indranil Sengupta, Prof. Sarani Bhattacharya, and Prof. Soumyajit Dey.
- 32-bit RISC architecture
- Custom Instruction Set Architecture (ISA) with 32 instructions
- Multi-cycle execution pipeline
- Implemented in Verilog HDL
- Optimized for Nexys A7-100T FPGA board
- ALU (Arithmetic Logic Unit)
- Control Unit
- Register File
- Memory Modules
- Python-based Assembler
The custom ISA includes:
- Arithmetic operations
- Bitwise operations
- Branch instructions
- Memory load-store operations
A custom assembler written in Python translates assembly code into machine instructions executable by the processor. It features:
- Mnemonic mapping for opcodes
- Support for all 32 instructions in the custom ISA
The processor is synthesized and implemented on a Nexys A7-100T FPGA board, demonstrating practical hardware deployment.
/verilog: Contains all Verilog HDL files for processor components/assembler: Python scripts for the custom assembler/docs: Documentation including ISA specifications and design details/testbenches: Verilog testbenches for component verification/fpga: Files specific to FPGA implementation
- Clone the repository
- Navigate to the
/verilogdirectory to view the processor implementation - Check the
/assemblerdirectory for the Python-based assembler - Refer to the documentation in
/docsfor detailed usage instructions
- Verilog HDL simulator (e.g., ModelSim, Icarus Verilog)
- Python 3.x for running the assembler
- Xilinx Vivado for FPGA synthesis and implementation
- Raj Parikh
- Sukhomay Patra
Special thanks to Prof. Indranil Sengupta, Prof. Sarani Bhattacharya, and Prof. Soumyajit Dey for their guidance throughout this project.