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[SRC][SRAM] Change sram to tc_sram_impl and wire the impl_i port …
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…as an input to the cluster.
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@DiyouS
DiyouS committed Nov 29, 2024
1 parent 9c715c5 commit dc45993
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Showing 6 changed files with 75 additions and 37 deletions.
4 changes: 2 additions & 2 deletions hw/ip/snitch_icache/src/snitch_icache.sv
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Expand Up @@ -64,8 +64,8 @@ module snitch_icache #(
output logic [NR_FETCH_PORTS-1:0] inst_ready_o,
output logic [NR_FETCH_PORTS-1:0] inst_error_o,

input sram_cfg_data_t sram_cfg_data_i,
input sram_cfg_tag_t sram_cfg_tag_i,
input sram_cfg_data_t [SET_COUNT-1:0] sram_cfg_data_i,
input sram_cfg_tag_t [SET_COUNT-1:0] sram_cfg_tag_i,

output axi_req_t axi_req_o,
input axi_rsp_t axi_rsp_i
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8 changes: 4 additions & 4 deletions hw/ip/snitch_icache/src/snitch_icache_lookup.sv
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Expand Up @@ -39,8 +39,8 @@ module snitch_icache_lookup #(
input logic write_valid_i,
output logic write_ready_o,

input sram_cfg_data_t sram_cfg_data_i,
input sram_cfg_tag_t sram_cfg_tag_i
input sram_cfg_data_t [CFG.SET_COUNT-1:0] sram_cfg_data_i,
input sram_cfg_tag_t [CFG.SET_COUNT-1:0] sram_cfg_tag_i
);

`ifndef SYNTHESIS
Expand Down Expand Up @@ -155,7 +155,7 @@ module snitch_icache_lookup #(
) i_tag (
.clk_i (clk_i),
.rst_ni (rst_ni),
.impl_i (sram_cfg_tag_i),
.impl_i (sram_cfg_tag_i[i]),
.impl_o ( ),
.req_i (ram_enable[i]),
.we_i (ram_write),
Expand All @@ -175,7 +175,7 @@ module snitch_icache_lookup #(
) i_data (
.clk_i (clk_i),
.rst_ni (rst_ni),
.impl_i (sram_cfg_data_i),
.impl_i (sram_cfg_data_i[i]),
.impl_o ( ),
.req_i (ram_enable[i]),
.we_i (ram_write),
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73 changes: 50 additions & 23 deletions hw/system/spatz_cluster/src/spatz_cluster.sv
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Expand Up @@ -93,12 +93,16 @@ module spatz_cluster
parameter type axi_in_resp_t = logic,
parameter type axi_out_req_t = logic,
parameter type axi_out_resp_t = logic,
/// SRAM configuration
parameter type impl_in_t = logic,
// Memory latency parameter. Most of the memories have a read latency of 1. In
// case you have memory macros which are pipelined you want to adjust this
// value here. This only applies to the TCDM. The instruction cache macros will break!
// In case you are using the `RegisterTCDMCuts` feature this adds an
// additional cycle latency, which is taken into account here.
parameter int unsigned MemoryMacroLatency = 1 + RegisterTCDMCuts
parameter int unsigned MemoryMacroLatency = 1 + RegisterTCDMCuts,
/// # SRAM Configuration rules needed: L1D Tag + L1D Data + L1D FIFO + L1I Tag + L1I Data
parameter int unsigned NrSramCfg = 64 + 8 + 1 + ICacheSets + ICacheSets
) (
/// System clock.
input logic clk_i,
Expand Down Expand Up @@ -136,7 +140,9 @@ module spatz_cluster
input axi_out_resp_t axi_out_resp_i,
/// AXI Core cluster out-port to L2 Mem.
output axi_out_req_t axi_out_l2_req_o,
input axi_out_resp_t axi_out_l2_resp_i
input axi_out_resp_t axi_out_l2_resp_i,
/// SRAM Configuration: L1D Data + L1D Tag + L1D FIFO + L1I Data + L1I Tag
input impl_in_t [NrSramCfg-1:0] impl_i
);
// ---------
// Imports
Expand Down Expand Up @@ -502,6 +508,17 @@ module spatz_cluster
logic l1d_busy;


// 9. SRAM Configuration
impl_in_t [L1NumWrapper-1:0][L1BankPerWP-1:0] impl_l1d_data;
impl_in_t [L1NumTagBank-1:0] impl_l1d_tag;
impl_in_t [1:0] impl_l1d_fifo;

impl_in_t [ICacheSets-1:0] impl_l1i_data;
impl_in_t [ICacheSets-1:0] impl_l1i_tag;

assign {impl_l1d_data, impl_l1d_tag, impl_l1d_fifo, impl_l1i_data, impl_l1i_tag} = impl_i;


// -------------
// DMA Subsystem
// -------------
Expand Down Expand Up @@ -708,26 +725,29 @@ module spatz_cluster
.NumWords (TCDMDepth ),
.ByteWidth (8 ),
.DataWidth (DataWidth ),
.MemoryResponseLatency (1 )
.MemoryResponseLatency (1 ),
.impl_in_t (impl_in_t )
) i_data_mem (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
.spm_size_i (cfg_spm_size ),
.clk_i (clk_i ),
.rst_ni (rst_ni ),
.spm_size_i (cfg_spm_size ),
/// Cache Side TODO: Connect cache
.cache_req_i (l1_cache_wp_req [j]),
.cache_we_i (l1_cache_wp_we [j]),
.cache_addr_i (l1_cache_wp_addr [j]),
.cache_wdata_i(l1_cache_wp_wdata[j]),
.cache_be_i (l1_cache_wp_be [j]),
.cache_rdata_o(l1_cache_wp_rdata[j]),
.cache_ready_o(l1_cache_wp_gnt [j]),
.cache_req_i (l1_cache_wp_req [j] ),
.cache_we_i (l1_cache_wp_we [j] ),
.cache_addr_i (l1_cache_wp_addr [j] ),
.cache_wdata_i(l1_cache_wp_wdata[j] ),
.cache_be_i (l1_cache_wp_be [j] ),
.cache_rdata_o(l1_cache_wp_rdata[j] ),
.cache_ready_o(l1_cache_wp_gnt [j] ),
/// SPM Side
.spm_req_i (mem_cs ),
.spm_we_i (mem_wen ),
.spm_req_i (mem_cs ),
.spm_we_i (mem_wen ),
.spm_addr_i (mem_add_max - mem_add),
.spm_wdata_i (mem_wdata ),
.spm_be_i (mem_be ),
.spm_rdata_o (mem_rdata )
.spm_wdata_i (mem_wdata ),
.spm_be_i (mem_be ),
.spm_rdata_o (mem_rdata ),
/// SRAM Configuration
.impl_i (impl_l1d_data[j] )
);

data_t amo_rdata_local;
Expand Down Expand Up @@ -862,11 +882,13 @@ module spatz_cluster
.BankFactor (L1BankFactor ),
// Type
.core_meta_t (tcdm_user_t ),
.impl_in_t (impl_in_t ),
.axi_req_t (axi_mst_dma_req_t ),
.axi_resp_t (axi_mst_dma_resp_t)
) i_l1_controller (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
.impl_i (impl_l1d_fifo ),
// Sync Control
.cache_sync_valid_i (l1d_insn_valid ),
.cache_sync_ready_o (l1d_insn_ready ),
Expand Down Expand Up @@ -909,16 +931,19 @@ module spatz_cluster
);

for (genvar j = 0; j < L1NumTagBank; j++) begin: gen_l1_tag_banks
tc_sram #(
tc_sram_impl #(
.NumWords (L1CacheWayEntry/L1BankFactor),
.DataWidth ($bits(data_t) ),
.ByteWidth ($bits(data_t) ),
.NumPorts (1 ),
.Latency (1 ),
.SimInit ("zeros" )
.SimInit ("zeros" ),
.impl_in_t (impl_in_t )
) i_meta_bank (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
.impl_i (impl_l1d_tag [j]),
.impl_o (/* unsed */ ),
.req_i (l1_tag_bank_req [j]),
.we_i (l1_tag_bank_we [j]),
.addr_i (l1_tag_bank_addr [j]),
Expand Down Expand Up @@ -1116,7 +1141,9 @@ module spatz_cluster
.L0_EARLY_TAG_WIDTH ( snitch_pkg::PAGE_SHIFT - $clog2(ICacheLineWidth/8) ),
.ISO_CROSSING ( 1'b0 ),
.axi_req_t ( axi_mst_dma_req_t ),
.axi_rsp_t ( axi_mst_dma_resp_t )
.axi_rsp_t ( axi_mst_dma_resp_t ),
.sram_cfg_data_t ( impl_in_t ),
.sram_cfg_tag_t ( impl_in_t )
) i_snitch_icache (
.clk_i ( clk_i ),
.clk_d2_i ( clk_i ),
Expand All @@ -1131,8 +1158,8 @@ module spatz_cluster
.inst_valid_i ( inst_valid ),
.inst_ready_o ( inst_ready ),
.inst_error_o ( inst_error ),
.sram_cfg_tag_i ( '0 ),
.sram_cfg_data_i ( '0 ),
.sram_cfg_tag_i ( impl_l1i_tag ),
.sram_cfg_data_i ( impl_l1i_data ),
.axi_req_o ( wide_axi_mst_req[ICache] ),
.axi_rsp_i ( wide_axi_mst_rsp[ICache] )
);
Expand Down
1 change: 1 addition & 0 deletions hw/system/spatz_cluster/src/spatz_cluster_wrapper.sv.tpl
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Original file line number Diff line number Diff line change
Expand Up @@ -561,6 +561,7 @@ module ${cfg['name']}_wrapper
) i_cluster (
.clk_i,
.rst_ni,
.impl_i( '0 ),
% if cfg['enable_debug']:
.debug_req_i,
% else:
Expand Down
24 changes: 16 additions & 8 deletions hw/system/spatz_cluster/src/spatz_sram_wrapper.sv
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Expand Up @@ -24,6 +24,8 @@ module spatz_sram_wrapper #(
parameter int unsigned MemAddrWidth = (NumWords > 32'd1) ? $clog2(NumWords) : 32'd1,
/// Address width of each bank
parameter int unsigned BankAddrWidth = MemAddrWidth - $clog2(NumBanks),
/// SRAM impl input type for configuration
parameter type impl_in_t = logic,
/// Address type of input (wrapper bank)
parameter type mem_addr_t = logic [MemAddrWidth-1:0],
/// Address type of data banks
Expand Down Expand Up @@ -55,7 +57,9 @@ module spatz_sram_wrapper #(
input mem_addr_t spm_addr_i,
input data_t spm_wdata_i,
input be_t spm_be_i,
output data_t spm_rdata_o
output data_t spm_rdata_o,
/// SRAM Control Signals
input impl_in_t [NumBanks-1:0] impl_i
);
typedef struct packed {
logic we;
Expand Down Expand Up @@ -150,16 +154,20 @@ module spatz_sram_wrapper #(
);

// Forward to bank
tc_sram #(
.NumWords (NumWords/NumBanks),
.DataWidth (DataWidth ),
.ByteWidth (ByteWidth ),
.NumPorts (1 ),
.Latency (MemoryResponseLatency ),
.SimInit ("zeros" )
tc_sram_impl #(
.NumWords (NumWords/NumBanks),
.DataWidth (DataWidth ),
.ByteWidth (ByteWidth ),
.NumPorts (1 ),
.Latency (MemoryResponseLatency ),
.SimInit ("zeros" ),
.impl_in_t (impl_in_t )
) i_data_bank (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// implementation-related
.impl_i (impl_i[i] ),
.impl_o (/* not used */ ),
.req_i (bank_valid[i] ),
.we_i (bank_req[i].we ),
.addr_i (bank_req[i].addr ),
Expand Down
2 changes: 2 additions & 0 deletions hw/system/spatz_cluster/tb/testbench.sv.tpl
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Expand Up @@ -205,6 +205,8 @@ module testharness (
% else:
.axi_out_req_o (axi_from_cluster_req ),
.axi_out_resp_i (axi_from_cluster_resp),
.axi_out_l2_req_o ( ),
.axi_out_l2_resp_i ('0),
.axi_in_req_i (axi_to_cluster_req ),
.axi_in_resp_o (axi_to_cluster_resp ),
% endif
Expand Down

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