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sw: fix Bender.yml
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Mattia Sinigaglia committed Jan 31, 2024
1 parent 9d3de99 commit d57a318
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184 changes: 74 additions & 110 deletions Bender.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,7 @@ package:
name: spatz
authors:
- "Matheus Cavalcante <[email protected]>"
- "Mattia Sinigaglia <[email protected]>"

dependencies:
axi: { git: "https://github.com/pulp-platform/axi.git", version: =0.39.1-beta }
Expand All @@ -18,9 +19,9 @@ dependencies:
tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.11 }

export_include_dirs:
- hw/ip/reqrsp_interface/include
- hw/ip/mem_interface/include
- hw/ip/snitch/include
- hw/ip/reqrsp_interface/include
- hw/ip/tcdm_interface/include

sources:
Expand Down Expand Up @@ -54,119 +55,82 @@ sources:
## hw/ip/mem_interface ##

- hw/ip/mem_interface/src/mem_wide_narrow_mux.sv
- hw/ip/mem_interface/src/mem_interface.sv

## hw/ip/tcdm_interface ##

# Level 0
- hw/ip/tcdm_interface/src/tcdm_interface.sv
# Level 1
- hw/ip/tcdm_interface/src/axi_to_tcdm.sv
- hw/ip/tcdm_interface/src/reqrsp_to_tcdm.sv
- hw/ip/tcdm_interface/src/tcdm_mux.sv
- target: simulation
files:
- hw/ip/mem_interface/src/mem_test.sv
- hw/ip/tcdm_interface/src/tcdm_test.sv
- target: test
files:
# Level 0
- hw/ip/mem_interface/test/mem_wide_narrow_mux_tb.sv
- hw/ip/tcdm_interface/test/reqrsp_to_tcdm_tb.sv
- hw/ip/tcdm_interface/test/tcdm_mux_tb.sv

## hw/ip/tcdm_interface ##
## hw/ip/snitch ##

# Level 0:
- hw/ip/snitch/src/snitch_pma_pkg.sv
- hw/ip/snitch/src/riscv_instr.sv
# Level 1:
- hw/ip/snitch/src/snitch_pkg.sv
# Level 2:
- hw/ip/snitch/src/snitch_regfile_ff.sv
# - hw/ip/snitch/src/snitch_regfile_fpga.sv
# - hw/ip/snitch/src/snitch_regfile_latch.sv
- hw/ip/snitch/src/snitch_lsu.sv
- hw/ip/snitch/src/snitch_l0_tlb.sv
# Level 1:
- target: not(disable_pmcs)
defines:
SNITCH_ENABLE_PERF:
files:
- hw/ip/snitch/src/snitch.sv
# Disable the performance monitoring counters to save area.
- target: disable_pmcs
files:
- hw/ip/snitch/src/snitch.sv

- target: test
files:
- hw/ip/snitch/test/snitch_l0_tlb_tb.sv

## hw/ip/snitch_icache ##

# Level 0:
- hw/ip/snitch_icache/src/snitch_icache_pkg.sv
# Level 1:
- hw/ip/snitch_icache/src/snitch_icache_l0.sv
- hw/ip/snitch_icache/src/snitch_icache_refill.sv
- hw/ip/snitch_icache/src/snitch_icache_lfsr.sv
- hw/ip/snitch_icache/src/snitch_icache_lookup.sv
# Level 2:
- hw/ip/snitch_icache/src/snitch_icache_handler.sv
# Level 3:
- hw/ip/snitch_icache/src/snitch_icache.sv
- target: test
files:
- hw/ip/snitch_icache/test/snitch_icache_l0_tb.sv

## hw/ip/snitch_test ##

# Level 1:
- target: any(simulation, verilator)
files:
- hw/ip/snitch_test/src/tb_memory_regbus.sv
# Level 2
- hw/ip/snitch_test/src/tb_memory_axi.sv
# Level 3:
- target: snitch_test
files:
- hw/ip/snitch_test/src/tb_bin.sv

# # Level 0:
# - hw/ip/reqrsp_interface/src/reqrsp_pkg.sv
# # Level 1:
# - hw/ip/reqrsp_interface/src/reqrsp_intf.sv
# # Level 2:
# - hw/ip/reqrsp_interface/src/axi_to_reqrsp.sv
# - hw/ip/reqrsp_interface/src/reqrsp_cut.sv
# - hw/ip/reqrsp_interface/src/reqrsp_demux.sv
# - hw/ip/reqrsp_interface/src/reqrsp_iso.sv
# - hw/ip/reqrsp_interface/src/reqrsp_mux.sv
# - hw/ip/reqrsp_interface/src/reqrsp_to_axi.sv
# - target: simulation
# files:
# - hw/ip/reqrsp_interface/src/reqrsp_test.sv
# - target: test
# files:
# # Level 0
# - hw/ip/reqrsp_interface/test/axi_to_reqrsp_tb.sv
# - hw/ip/reqrsp_interface/test/reqrsp_demux_tb.sv
# - hw/ip/reqrsp_interface/test/reqrsp_idempotent_tb.sv
# - hw/ip/reqrsp_interface/test/reqrsp_mux_tb.sv
# - hw/ip/reqrsp_interface/test/reqrsp_to_axi_tb.sv

# ## hw/ip/mem_interface ##

- hw/ip/mem_interface/src/mem_wide_narrow_mux.sv

## hw/ip/tcdm_interface ##

# # Level 0
# - hw/ip/tcdm_interface/src/tcdm_interface.sv
# # Level 1
# - hw/ip/tcdm_interface/src/axi_to_tcdm.sv
# - hw/ip/tcdm_interface/src/reqrsp_to_tcdm.sv
# - hw/ip/tcdm_interface/src/tcdm_mux.sv
# - target: simulation
# files:
# - hw/ip/tcdm_interface/src/tcdm_test.sv
# - target: test
# files:
# # Level 0
# - hw/ip/tcdm_interface/test/reqrsp_to_tcdm_tb.sv
# - hw/ip/tcdm_interface/test/tcdm_mux_tb.sv

# Use Mempool snitch
# ## hw/ip/snitch ##

# # Level 0:
# - hw/ip/snitch/src/snitch_pma_pkg.sv
# - hw/ip/snitch/src/riscv_instr.sv
# # Level 1:
# - hw/ip/snitch/src/snitch_pkg.sv
# # Level 2:
# - hw/ip/snitch/src/snitch_regfile_ff.sv
# # - hw/ip/snitch/src/snitch_regfile_fpga.sv
# # - hw/ip/snitch/src/snitch_regfile_latch.sv
# - hw/ip/snitch/src/snitch_lsu.sv
# - hw/ip/snitch/src/snitch_l0_tlb.sv
# # Level 1:
# - target: not(disable_pmcs)
# defines:
# SNITCH_ENABLE_PERF:
# files:
# - hw/ip/snitch/src/snitch.sv
# # Disable the performance monitoring counters to save area.
# - target: disable_pmcs
# files:
# - hw/ip/snitch/src/snitch.sv

# - target: test
# files:
# - hw/ip/snitch/test/snitch_l0_tlb_tb.sv

# ## hw/ip/snitch_icache ##

# # Level 0:
# - hw/ip/snitch_icache/src/snitch_icache_pkg.sv
# # Level 1:
# - hw/ip/snitch_icache/src/snitch_icache_l0.sv
# - hw/ip/snitch_icache/src/snitch_icache_refill.sv
# - hw/ip/snitch_icache/src/snitch_icache_lfsr.sv
# - hw/ip/snitch_icache/src/snitch_icache_lookup.sv
# # Level 2:
# - hw/ip/snitch_icache/src/snitch_icache_handler.sv
# # Level 3:
# - hw/ip/snitch_icache/src/snitch_icache.sv
# - target: test
# files:
# - hw/ip/snitch_icache/test/snitch_icache_l0_tb.sv

# ## hw/ip/snitch_test ##

# # Level 1:
# - target: any(simulation, verilator)
# files:
# - hw/ip/snitch_test/src/tb_memory_regbus.sv
# # Level 2
# - hw/ip/snitch_test/src/tb_memory_axi.sv
# # Level 3:
# - target: snitch_test
# files:
# - hw/ip/snitch_test/src/tb_bin.sv

## hw/ip/spatz ##
- target: spatz
Expand All @@ -176,7 +140,6 @@ sources:
- hw/ip/spatz/src/rvv_pkg.sv
# Level 1
- hw/ip/spatz/src/generated/spatz_pkg.sv

- hw/ip/spatz/src/spatz_serdiv.sv
# Level 2
- hw/ip/spatz/src/spatz_decoder.sv
Expand All @@ -198,6 +161,7 @@ sources:
files:
- hw/ip/spatz_cc/src/spatz_mempool_cc.sv


## hw/ip/spatz_cc ##
- target: not(mempool)
files:
Expand Down Expand Up @@ -230,5 +194,5 @@ sources:

- target: spatz_test
files:
# Level 1
- hw/system/spatz_cluster/tb/testharness.sv
# Level 1
- hw/system/spatz_cluster/tb/testharness.sv
6 changes: 5 additions & 1 deletion hw/ip/spatz_cc/src/spatz_mempool_cc.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -257,7 +257,7 @@ module spatz_mempool_cc

// TODO: Perhaps put it into a module
// Assign TCDM data interface
for (genvar i = 0; i < NumMemPortsPerSpatz; i++) begin
for (genvar i = 0; i < NumMemPortsPerSpatz; i++) begin : gen_tcdm_assignment
assign data_qaddr_o[i+1] = spatz_mem_req[i].addr;
assign data_qwrite_o[i+1] = spatz_mem_req[i].write;
assign data_qamo_o[i+1] = '0;
Expand Down Expand Up @@ -382,6 +382,7 @@ module spatz_mempool_cc
logic [63:0] cycle;
int unsigned stall, stall_ins, stall_raw, stall_lsu, stall_acc;

// verilog_lint: waive-start always-ff-non-blocking
always_ff @(posedge rst_i) begin
if(rst_i) begin
// Format in hex because vcs and vsim treat decimal differently
Expand All @@ -391,10 +392,12 @@ module spatz_mempool_cc
$display("[Tracer] Logging Hart %d to %s", hart_id_i, fn);
end
end
// verilog_lint: waive-stop always-ff-non-blocking

typedef enum logic [1:0] {SrcSnitch = 0, SrcFpu = 1, SrcFpuSeq = 2} trace_src_e;
localparam int SnitchTrace = `ifdef SNITCH_TRACE `SNITCH_TRACE `else 0 `endif;

// verilog_lint: waive-start always-ff-non-blocking
always_ff @(posedge clk_i or posedge rst_i) begin
automatic string trace_entry;
automatic string extras_str;
Expand Down Expand Up @@ -494,6 +497,7 @@ module spatz_mempool_cc
final begin
$fclose(f);
end
// verilog_lint: waive-stop always-ff-non-blocking
// pragma translate_on

endmodule

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