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[SRC][VLSU] WIP: Add status for each port in VLSU to avoid mishandlin…
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…g when ports are racing to switch from store status to load status. Currently still have bugs in cache-based fft kernel.

Remove CDC generated in wrapper for flamingo configuration (will be added in top level instead).
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@DiyouS
DiyouS committed Nov 11, 2024
1 parent 6cf617e commit d04eeae
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Showing 2 changed files with 45 additions and 13 deletions.
54 changes: 43 additions & 11 deletions hw/ip/spatz/src/spatz_vlsu.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -164,15 +164,25 @@ module spatz_vlsu
// State //
/////////////

enum logic {
typedef enum logic {
VLSU_RunningLoad, VLSU_RunningStore
} state_d, state_q;
} state_t;
state_t state_d, state_q;
`FF(state_q, state_d, VLSU_RunningLoad)

state_t [NrMemPorts-1:0] port_state_d, port_state_q;
for (genvar port = 0; port < NrMemPorts; port++) begin: gen_port_state_q
`FF(port_state_q[port], port_state_d[port], VLSU_RunningLoad)
end: gen_port_state_q

id_t [NrMemPorts-1:0] store_count_q;
id_t [NrMemPorts-1:0] store_count_d;

// Memory requests
spatz_mem_req_t [NrMemPorts-1:0] spatz_mem_req;
logic [NrMemPorts-1:0] spatz_mem_req_valid;
logic [NrMemPorts-1:0] spatz_mem_req_ready;

for (genvar port = 0; port < NrMemPorts; port++) begin: gen_store_count_q
`FF(store_count_q[port], store_count_d[port], '0)
end: gen_store_count_q
Expand All @@ -182,7 +192,11 @@ module spatz_vlsu
store_count_d = store_count_q;

for (int port = 0; port < NrMemPorts; port++) begin
if (spatz_mem_req_o[port].write && spatz_mem_req_valid_o[port] && spatz_mem_req_ready_i[port])
// if (spatz_mem_req_o[port].write && spatz_mem_req_valid_o[port] && spatz_mem_req_ready_i[port])
// // Did we send a store?
// store_count_d[port]++;
// We need to count a store once it is sent to reg for correct handling
if (spatz_mem_req[port].write && spatz_mem_req_valid[port] && spatz_mem_req_ready[port])
// Did we send a store?
store_count_d[port]++;

Expand Down Expand Up @@ -578,10 +592,10 @@ module spatz_vlsu
// Did we finish an instruction?
logic vlsu_finished_req;

// Memory requests
spatz_mem_req_t [NrMemPorts-1:0] spatz_mem_req;
logic [NrMemPorts-1:0] spatz_mem_req_valid;
logic [NrMemPorts-1:0] spatz_mem_req_ready;
// // Memory requests
// spatz_mem_req_t [NrMemPorts-1:0] spatz_mem_req;
// logic [NrMemPorts-1:0] spatz_mem_req_valid;
// logic [NrMemPorts-1:0] spatz_mem_req_ready;

always_comb begin: control_proc
// Maintain state
Expand Down Expand Up @@ -753,7 +767,8 @@ module spatz_vlsu
commit_operation_valid[fu] = commit_insn_valid && (commit_counter_q[fu] != max_elements) && (catchup[fu] || (!catchup[fu] && ~|catchup));

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[verible-verilog-lint] hw/ip/spatz/src/spatz_vlsu.sv#L767 

Line length exceeds max: 100; is: 143 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 143 [Style: line-length] [line-length]" location:{path:"hw/ip/spatz/src/spatz_vlsu.sv" range:{start:{line:767 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
commit_operation_last[fu] = commit_operation_valid[fu] && ((max_elements - commit_counter_q[fu]) <= (commit_is_single_element_operation ? commit_single_element_size : ELENB));

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[verible-verilog-lint] hw/ip/spatz/src/spatz_vlsu.sv#L768 

Line length exceeds max: 100; is: 182 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 182 [Style: line-length] [line-length]" location:{path:"hw/ip/spatz/src/spatz_vlsu.sv" range:{start:{line:768 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
commit_counter_delta[fu] = !commit_operation_valid[fu] ? vlen_t'('d0) : commit_is_single_element_operation ? vlen_t'(commit_single_element_size) : commit_operation_last[fu] ? (max_elements - commit_counter_q[fu]) : vlen_t'(ELENB);

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[verible-verilog-lint] hw/ip/spatz/src/spatz_vlsu.sv#L769 

Line length exceeds max: 100; is: 238 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 238 [Style: line-length] [line-length]" location:{path:"hw/ip/spatz/src/spatz_vlsu.sv" range:{start:{line:769 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
commit_counter_en[fu] = commit_operation_valid[fu] && (commit_insn_q.is_load && vrf_req_valid_d && vrf_req_ready_d) || (!commit_insn_q.is_load && vrf_rvalid_i[0] && vrf_re_o[0] && (!mem_is_indexed || vrf_rvalid_i[1]));
commit_counter_en[fu] = commit_operation_valid[fu] && (commit_insn_q.is_load && vrf_req_valid_d && vrf_req_ready_d) && (port_state_q == VLSU_RunningLoad)||

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[verible-verilog-lint] hw/ip/spatz/src/spatz_vlsu.sv#L770 

Line length exceeds max: 100; is: 166 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 166 [Style: line-length] [line-length]" location:{path:"hw/ip/spatz/src/spatz_vlsu.sv" range:{start:{line:770 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
(!commit_insn_q.is_load && vrf_rvalid_i[0] && vrf_re_o[0] && (!mem_is_indexed || vrf_rvalid_i[1]));

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[verible-verilog-lint] hw/ip/spatz/src/spatz_vlsu.sv#L771 

Line length exceeds max: 100; is: 134 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 134 [Style: line-length] [line-length]" location:{path:"hw/ip/spatz/src/spatz_vlsu.sv" range:{start:{line:771 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
commit_counter_max[fu] = max_elements;
end
end
Expand Down Expand Up @@ -804,6 +819,24 @@ module spatz_vlsu
always_comb begin: p_state
// Maintain state
state_d = state_q;
for (int port = 0; port < NrMemPorts; port++) begin
port_state_d[port] = port_state_q[port];
unique case (port_state_q[port])
VLSU_RunningLoad: begin
if (commit_insn_valid && !commit_insn_q.is_load)
if (rob_empty[port])
port_state_d[port] = VLSU_RunningStore;
end

// Do not switch mode until all store requests are actually sent
VLSU_RunningStore: begin
if (spatz_mem_req_valid_o[port])
port_state_d[port] = spatz_mem_req_o[port].write ? VLSU_RunningStore : VLSU_RunningLoad;
end

default:;
endcase
end

unique case (state_q)
VLSU_RunningLoad: begin
Expand Down Expand Up @@ -1052,8 +1085,7 @@ module spatz_vlsu
mem_req_svalid[port] = rob_rvalid[port] && (!mem_is_indexed || (vrf_rvalid_i[1] && !pending_index[port])) && !mem_spatz_req.op_mem.is_load;

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[verible-verilog-lint] hw/ip/spatz/src/spatz_vlsu.sv#L1085 

Line length exceeds max: 100; is: 149 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 149 [Style: line-length] [line-length]" location:{path:"hw/ip/spatz/src/spatz_vlsu.sv" range:{start:{line:1085 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
mem_req_id[port] = rob_rid[port];
mem_req_last[port] = mem_operation_last[port];
rob_pop[port] = spatz_mem_req_valid[port] && spatz_mem_req_ready[port];
store_flag[port] = 1'b1;
rob_pop[port] = spatz_mem_req_valid[port] && spatz_mem_req_ready[port];

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[verible-verilog-lint] hw/ip/spatz/src/spatz_vlsu.sv#L1088 

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output 
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"hw/ip/spatz/src/spatz_vlsu.sv" range:{start:{line:1088 column:89}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:1088 column:89} end:{line:1089}} text:"          rob_pop[port]        = spatz_mem_req_valid[port] && spatz_mem_req_ready[port];\n"}

// Create byte enable signal for memory request
if (mem_is_single_element_operation) begin
Expand All @@ -1071,7 +1103,7 @@ module spatz_vlsu
mem_req_strb[port][k] = k < mem_counter_delta[port];
end else begin
spatz_mem_rsp_ready_o[port] = 1'b0;
clear_flag[port] = 1'b1;
// clear_flag[port] = 1'b1;

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[verible-verilog-lint] hw/ip/spatz/src/spatz_vlsu.sv#L1107 

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output 
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"hw/ip/spatz/src/spatz_vlsu.sv" range:{start:{line:1107 column:1}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:1107 column:1} end:{line:1108}} text:"\n"}
// // Clear empty buffer id requests
// if (!rob_empty[port]) begin
Expand Down
4 changes: 2 additions & 2 deletions hw/system/spatz_cluster/cfg/flamingo.hjson
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Original file line number Diff line number Diff line change
Expand Up @@ -15,9 +15,9 @@
id_width_in: 6,
id_width_out: 2,
user_width: 10,
axi_cdc_enable: true,
axi_cdc_enable: false,
sw_rst_enable: true,
axi_isolate_enable: true,
axi_isolate_enable: false,
tcdm: {
size: 32,
banks: 8,
Expand Down

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