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[CSR] Add cycle count CSR for Flamingo toplevel and update software c…
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@DiyouS
DiyouS committed Dec 13, 2024
1 parent 6450d7f commit 6709d07
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12 changes: 12 additions & 0 deletions hw/system/spatz_cluster/src/spatz_cluster_peripheral/spatz_cluster_peripheral_reg.hjson
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Original file line number Diff line number Diff line change
Expand Up @@ -415,6 +415,18 @@
desc: "Indicates the cluster is computing a kernel."
}]
},
{
name: "SPATZ_CYCLE",
desc: '''Store cycle counts of kernels'''
swaccess: "rw",
hwaccess: "hrw",
resval: "0",
fields: [{
bits: "31:0",
name: "SPATZ_CYC",
desc: "Store cycle counts of kernels."
}]
},
{
name: "CLUSTER_BOOT_CONTROL",
desc: '''Controls the cluster boot process.'''
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64 changes: 39 additions & 25 deletions hw/system/spatz_cluster/src/spatz_cluster_peripheral/spatz_cluster_peripheral_reg_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -143,6 +143,10 @@ package spatz_cluster_peripheral_reg_pkg;
logic q;
} spatz_cluster_peripheral_reg2hw_spatz_status_reg_t;

typedef struct packed {
logic [31:0] q;
} spatz_cluster_peripheral_reg2hw_spatz_cycle_reg_t;

typedef struct packed {
logic [31:0] q;
} spatz_cluster_peripheral_reg2hw_cluster_boot_control_reg_t;
Expand Down Expand Up @@ -175,6 +179,11 @@ package spatz_cluster_peripheral_reg_pkg;
logic [31:0] d;
} spatz_cluster_peripheral_hw2reg_hw_barrier_reg_t;

typedef struct packed {
logic [31:0] d;
logic de;
} spatz_cluster_peripheral_hw2reg_spatz_cycle_reg_t;

typedef struct packed {
logic d;
logic de;
Expand All @@ -191,14 +200,15 @@ package spatz_cluster_peripheral_reg_pkg;

// Register -> HW type
typedef struct packed {
spatz_cluster_peripheral_reg2hw_perf_counter_enable_mreg_t [1:0] perf_counter_enable; // [326:265]
spatz_cluster_peripheral_reg2hw_hart_select_mreg_t [1:0] hart_select; // [264:245]
spatz_cluster_peripheral_reg2hw_perf_counter_mreg_t [1:0] perf_counter; // [244:147]
spatz_cluster_peripheral_reg2hw_cl_clint_set_reg_t cl_clint_set; // [146:114]
spatz_cluster_peripheral_reg2hw_cl_clint_clear_reg_t cl_clint_clear; // [113:81]
spatz_cluster_peripheral_reg2hw_hw_barrier_reg_t hw_barrier; // [80:49]
spatz_cluster_peripheral_reg2hw_icache_prefetch_enable_reg_t icache_prefetch_enable; // [48:48]
spatz_cluster_peripheral_reg2hw_spatz_status_reg_t spatz_status; // [47:47]
spatz_cluster_peripheral_reg2hw_perf_counter_enable_mreg_t [1:0] perf_counter_enable; // [358:297]
spatz_cluster_peripheral_reg2hw_hart_select_mreg_t [1:0] hart_select; // [296:277]
spatz_cluster_peripheral_reg2hw_perf_counter_mreg_t [1:0] perf_counter; // [276:179]
spatz_cluster_peripheral_reg2hw_cl_clint_set_reg_t cl_clint_set; // [178:146]
spatz_cluster_peripheral_reg2hw_cl_clint_clear_reg_t cl_clint_clear; // [145:113]
spatz_cluster_peripheral_reg2hw_hw_barrier_reg_t hw_barrier; // [112:81]
spatz_cluster_peripheral_reg2hw_icache_prefetch_enable_reg_t icache_prefetch_enable; // [80:80]
spatz_cluster_peripheral_reg2hw_spatz_status_reg_t spatz_status; // [79:79]
spatz_cluster_peripheral_reg2hw_spatz_cycle_reg_t spatz_cycle; // [78:47]
spatz_cluster_peripheral_reg2hw_cluster_boot_control_reg_t cluster_boot_control; // [46:15]
spatz_cluster_peripheral_reg2hw_cluster_eoc_exit_reg_t cluster_eoc_exit; // [14:14]
spatz_cluster_peripheral_reg2hw_cfg_l1d_spm_reg_t cfg_l1d_spm; // [13:4]
Expand All @@ -209,8 +219,9 @@ package spatz_cluster_peripheral_reg_pkg;

// HW -> register type
typedef struct packed {
spatz_cluster_peripheral_hw2reg_perf_counter_mreg_t [1:0] perf_counter; // [132:37]
spatz_cluster_peripheral_hw2reg_hw_barrier_reg_t hw_barrier; // [36:5]
spatz_cluster_peripheral_hw2reg_perf_counter_mreg_t [1:0] perf_counter; // [165:70]
spatz_cluster_peripheral_hw2reg_hw_barrier_reg_t hw_barrier; // [69:38]
spatz_cluster_peripheral_hw2reg_spatz_cycle_reg_t spatz_cycle; // [37:5]
spatz_cluster_peripheral_hw2reg_l1d_spm_commit_reg_t l1d_spm_commit; // [4:3]
spatz_cluster_peripheral_hw2reg_l1d_insn_commit_reg_t l1d_insn_commit; // [2:1]
spatz_cluster_peripheral_hw2reg_l1d_flush_status_reg_t l1d_flush_status; // [0:0]
Expand All @@ -228,13 +239,14 @@ package spatz_cluster_peripheral_reg_pkg;
parameter logic [BlockAw-1:0] SPATZ_CLUSTER_PERIPHERAL_HW_BARRIER_OFFSET = 8'h 40;
parameter logic [BlockAw-1:0] SPATZ_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE_OFFSET = 8'h 48;
parameter logic [BlockAw-1:0] SPATZ_CLUSTER_PERIPHERAL_SPATZ_STATUS_OFFSET = 8'h 50;
parameter logic [BlockAw-1:0] SPATZ_CLUSTER_PERIPHERAL_CLUSTER_BOOT_CONTROL_OFFSET = 8'h 58;
parameter logic [BlockAw-1:0] SPATZ_CLUSTER_PERIPHERAL_CLUSTER_EOC_EXIT_OFFSET = 8'h 60;
parameter logic [BlockAw-1:0] SPATZ_CLUSTER_PERIPHERAL_CFG_L1D_SPM_OFFSET = 8'h 68;
parameter logic [BlockAw-1:0] SPATZ_CLUSTER_PERIPHERAL_CFG_L1D_INSN_OFFSET = 8'h 70;
parameter logic [BlockAw-1:0] SPATZ_CLUSTER_PERIPHERAL_L1D_SPM_COMMIT_OFFSET = 8'h 78;
parameter logic [BlockAw-1:0] SPATZ_CLUSTER_PERIPHERAL_L1D_INSN_COMMIT_OFFSET = 8'h 80;
parameter logic [BlockAw-1:0] SPATZ_CLUSTER_PERIPHERAL_L1D_FLUSH_STATUS_OFFSET = 8'h 88;
parameter logic [BlockAw-1:0] SPATZ_CLUSTER_PERIPHERAL_SPATZ_CYCLE_OFFSET = 8'h 58;
parameter logic [BlockAw-1:0] SPATZ_CLUSTER_PERIPHERAL_CLUSTER_BOOT_CONTROL_OFFSET = 8'h 60;
parameter logic [BlockAw-1:0] SPATZ_CLUSTER_PERIPHERAL_CLUSTER_EOC_EXIT_OFFSET = 8'h 68;
parameter logic [BlockAw-1:0] SPATZ_CLUSTER_PERIPHERAL_CFG_L1D_SPM_OFFSET = 8'h 70;
parameter logic [BlockAw-1:0] SPATZ_CLUSTER_PERIPHERAL_CFG_L1D_INSN_OFFSET = 8'h 78;
parameter logic [BlockAw-1:0] SPATZ_CLUSTER_PERIPHERAL_L1D_SPM_COMMIT_OFFSET = 8'h 80;
parameter logic [BlockAw-1:0] SPATZ_CLUSTER_PERIPHERAL_L1D_INSN_COMMIT_OFFSET = 8'h 88;
parameter logic [BlockAw-1:0] SPATZ_CLUSTER_PERIPHERAL_L1D_FLUSH_STATUS_OFFSET = 8'h 90;

// Reset values for hwext registers and their fields
parameter logic [47:0] SPATZ_CLUSTER_PERIPHERAL_PERF_COUNTER_0_RESVAL = 48'h 0;
Expand All @@ -258,6 +270,7 @@ package spatz_cluster_peripheral_reg_pkg;
SPATZ_CLUSTER_PERIPHERAL_HW_BARRIER,
SPATZ_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE,
SPATZ_CLUSTER_PERIPHERAL_SPATZ_STATUS,
SPATZ_CLUSTER_PERIPHERAL_SPATZ_CYCLE,
SPATZ_CLUSTER_PERIPHERAL_CLUSTER_BOOT_CONTROL,
SPATZ_CLUSTER_PERIPHERAL_CLUSTER_EOC_EXIT,
SPATZ_CLUSTER_PERIPHERAL_CFG_L1D_SPM,
Expand All @@ -268,7 +281,7 @@ package spatz_cluster_peripheral_reg_pkg;
} spatz_cluster_peripheral_id_e;

// Register width information to check illegal writes
parameter logic [3:0] SPATZ_CLUSTER_PERIPHERAL_PERMIT [18] = '{
parameter logic [3:0] SPATZ_CLUSTER_PERIPHERAL_PERMIT [19] = '{
4'b 1111, // index[ 0] SPATZ_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0
4'b 1111, // index[ 1] SPATZ_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1
4'b 0011, // index[ 2] SPATZ_CLUSTER_PERIPHERAL_HART_SELECT_0
Expand All @@ -280,13 +293,14 @@ package spatz_cluster_peripheral_reg_pkg;
4'b 1111, // index[ 8] SPATZ_CLUSTER_PERIPHERAL_HW_BARRIER
4'b 0001, // index[ 9] SPATZ_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE
4'b 0001, // index[10] SPATZ_CLUSTER_PERIPHERAL_SPATZ_STATUS
4'b 1111, // index[11] SPATZ_CLUSTER_PERIPHERAL_CLUSTER_BOOT_CONTROL
4'b 0001, // index[12] SPATZ_CLUSTER_PERIPHERAL_CLUSTER_EOC_EXIT
4'b 0011, // index[13] SPATZ_CLUSTER_PERIPHERAL_CFG_L1D_SPM
4'b 0001, // index[14] SPATZ_CLUSTER_PERIPHERAL_CFG_L1D_INSN
4'b 0001, // index[15] SPATZ_CLUSTER_PERIPHERAL_L1D_SPM_COMMIT
4'b 0001, // index[16] SPATZ_CLUSTER_PERIPHERAL_L1D_INSN_COMMIT
4'b 0001 // index[17] SPATZ_CLUSTER_PERIPHERAL_L1D_FLUSH_STATUS
4'b 1111, // index[11] SPATZ_CLUSTER_PERIPHERAL_SPATZ_CYCLE
4'b 1111, // index[12] SPATZ_CLUSTER_PERIPHERAL_CLUSTER_BOOT_CONTROL
4'b 0001, // index[13] SPATZ_CLUSTER_PERIPHERAL_CLUSTER_EOC_EXIT
4'b 0011, // index[14] SPATZ_CLUSTER_PERIPHERAL_CFG_L1D_SPM
4'b 0001, // index[15] SPATZ_CLUSTER_PERIPHERAL_CFG_L1D_INSN
4'b 0001, // index[16] SPATZ_CLUSTER_PERIPHERAL_L1D_SPM_COMMIT
4'b 0001, // index[17] SPATZ_CLUSTER_PERIPHERAL_L1D_INSN_COMMIT
4'b 0001 // index[18] SPATZ_CLUSTER_PERIPHERAL_L1D_FLUSH_STATUS
};

endpackage
Expand Down
83 changes: 61 additions & 22 deletions hw/system/spatz_cluster/src/spatz_cluster_peripheral/spatz_cluster_peripheral_reg_top.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -278,6 +278,9 @@ module spatz_cluster_peripheral_reg_top #(
logic icache_prefetch_enable_we;
logic spatz_status_wd;
logic spatz_status_we;
logic [31:0] spatz_cycle_qs;
logic [31:0] spatz_cycle_wd;
logic spatz_cycle_we;
logic [31:0] cluster_boot_control_qs;
logic [31:0] cluster_boot_control_wd;
logic cluster_boot_control_we;
Expand Down Expand Up @@ -2110,6 +2113,33 @@ module spatz_cluster_peripheral_reg_top #(
);


// R[spatz_cycle]: V(False)

prim_subreg #(
.DW (32),
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_spatz_cycle (
.clk_i (clk_i ),
.rst_ni (rst_ni ),

// from register interface
.we (spatz_cycle_we),
.wd (spatz_cycle_wd),

// from internal hardware
.de (hw2reg.spatz_cycle.de),
.d (hw2reg.spatz_cycle.d ),

// to internal hardware
.qe (),
.q (reg2hw.spatz_cycle.q ),

// to register interface (read)
.qs (spatz_cycle_qs)
);


// R[cluster_boot_control]: V(False)

prim_subreg #(
Expand Down Expand Up @@ -2290,7 +2320,7 @@ module spatz_cluster_peripheral_reg_top #(



logic [17:0] addr_hit;
logic [18:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[ 0] = (reg_addr == SPATZ_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_OFFSET);
Expand All @@ -2304,13 +2334,14 @@ module spatz_cluster_peripheral_reg_top #(
addr_hit[ 8] = (reg_addr == SPATZ_CLUSTER_PERIPHERAL_HW_BARRIER_OFFSET);
addr_hit[ 9] = (reg_addr == SPATZ_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE_OFFSET);
addr_hit[10] = (reg_addr == SPATZ_CLUSTER_PERIPHERAL_SPATZ_STATUS_OFFSET);
addr_hit[11] = (reg_addr == SPATZ_CLUSTER_PERIPHERAL_CLUSTER_BOOT_CONTROL_OFFSET);
addr_hit[12] = (reg_addr == SPATZ_CLUSTER_PERIPHERAL_CLUSTER_EOC_EXIT_OFFSET);
addr_hit[13] = (reg_addr == SPATZ_CLUSTER_PERIPHERAL_CFG_L1D_SPM_OFFSET);
addr_hit[14] = (reg_addr == SPATZ_CLUSTER_PERIPHERAL_CFG_L1D_INSN_OFFSET);
addr_hit[15] = (reg_addr == SPATZ_CLUSTER_PERIPHERAL_L1D_SPM_COMMIT_OFFSET);
addr_hit[16] = (reg_addr == SPATZ_CLUSTER_PERIPHERAL_L1D_INSN_COMMIT_OFFSET);
addr_hit[17] = (reg_addr == SPATZ_CLUSTER_PERIPHERAL_L1D_FLUSH_STATUS_OFFSET);
addr_hit[11] = (reg_addr == SPATZ_CLUSTER_PERIPHERAL_SPATZ_CYCLE_OFFSET);
addr_hit[12] = (reg_addr == SPATZ_CLUSTER_PERIPHERAL_CLUSTER_BOOT_CONTROL_OFFSET);
addr_hit[13] = (reg_addr == SPATZ_CLUSTER_PERIPHERAL_CLUSTER_EOC_EXIT_OFFSET);
addr_hit[14] = (reg_addr == SPATZ_CLUSTER_PERIPHERAL_CFG_L1D_SPM_OFFSET);
addr_hit[15] = (reg_addr == SPATZ_CLUSTER_PERIPHERAL_CFG_L1D_INSN_OFFSET);
addr_hit[16] = (reg_addr == SPATZ_CLUSTER_PERIPHERAL_L1D_SPM_COMMIT_OFFSET);
addr_hit[17] = (reg_addr == SPATZ_CLUSTER_PERIPHERAL_L1D_INSN_COMMIT_OFFSET);
addr_hit[18] = (reg_addr == SPATZ_CLUSTER_PERIPHERAL_L1D_FLUSH_STATUS_OFFSET);
end

assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
Expand All @@ -2335,7 +2366,8 @@ module spatz_cluster_peripheral_reg_top #(
(addr_hit[14] & (|(SPATZ_CLUSTER_PERIPHERAL_PERMIT[14] & ~reg_be))) |
(addr_hit[15] & (|(SPATZ_CLUSTER_PERIPHERAL_PERMIT[15] & ~reg_be))) |
(addr_hit[16] & (|(SPATZ_CLUSTER_PERIPHERAL_PERMIT[16] & ~reg_be))) |
(addr_hit[17] & (|(SPATZ_CLUSTER_PERIPHERAL_PERMIT[17] & ~reg_be)))));
(addr_hit[17] & (|(SPATZ_CLUSTER_PERIPHERAL_PERMIT[17] & ~reg_be))) |
(addr_hit[18] & (|(SPATZ_CLUSTER_PERIPHERAL_PERMIT[18] & ~reg_be)))));
end

assign perf_counter_enable_0_cycle_0_we = addr_hit[0] & reg_we & !reg_error;
Expand Down Expand Up @@ -2552,25 +2584,28 @@ module spatz_cluster_peripheral_reg_top #(
assign spatz_status_we = addr_hit[10] & reg_we & !reg_error;
assign spatz_status_wd = reg_wdata[0];

assign cluster_boot_control_we = addr_hit[11] & reg_we & !reg_error;
assign spatz_cycle_we = addr_hit[11] & reg_we & !reg_error;
assign spatz_cycle_wd = reg_wdata[31:0];

assign cluster_boot_control_we = addr_hit[12] & reg_we & !reg_error;
assign cluster_boot_control_wd = reg_wdata[31:0];

assign cluster_eoc_exit_we = addr_hit[12] & reg_we & !reg_error;
assign cluster_eoc_exit_we = addr_hit[13] & reg_we & !reg_error;
assign cluster_eoc_exit_wd = reg_wdata[0];

assign cfg_l1d_spm_we = addr_hit[13] & reg_we & !reg_error;
assign cfg_l1d_spm_we = addr_hit[14] & reg_we & !reg_error;
assign cfg_l1d_spm_wd = reg_wdata[9:0];

assign cfg_l1d_insn_we = addr_hit[14] & reg_we & !reg_error;
assign cfg_l1d_insn_we = addr_hit[15] & reg_we & !reg_error;
assign cfg_l1d_insn_wd = reg_wdata[1:0];

assign l1d_spm_commit_we = addr_hit[15] & reg_we & !reg_error;
assign l1d_spm_commit_we = addr_hit[16] & reg_we & !reg_error;
assign l1d_spm_commit_wd = reg_wdata[0];

assign l1d_insn_commit_we = addr_hit[16] & reg_we & !reg_error;
assign l1d_insn_commit_we = addr_hit[17] & reg_we & !reg_error;
assign l1d_insn_commit_wd = reg_wdata[0];

assign l1d_flush_status_re = addr_hit[17] & reg_re & !reg_error;
assign l1d_flush_status_re = addr_hit[18] & reg_re & !reg_error;

// Read data return
always_comb begin
Expand Down Expand Up @@ -2681,30 +2716,34 @@ module spatz_cluster_peripheral_reg_top #(
end

addr_hit[11]: begin
reg_rdata_next[31:0] = cluster_boot_control_qs;
reg_rdata_next[31:0] = spatz_cycle_qs;
end

addr_hit[12]: begin
reg_rdata_next[0] = cluster_eoc_exit_qs;
reg_rdata_next[31:0] = cluster_boot_control_qs;
end

addr_hit[13]: begin
reg_rdata_next[9:0] = cfg_l1d_spm_qs;
reg_rdata_next[0] = cluster_eoc_exit_qs;
end

addr_hit[14]: begin
reg_rdata_next[1:0] = cfg_l1d_insn_qs;
reg_rdata_next[9:0] = cfg_l1d_spm_qs;
end

addr_hit[15]: begin
reg_rdata_next[0] = l1d_spm_commit_qs;
reg_rdata_next[1:0] = cfg_l1d_insn_qs;
end

addr_hit[16]: begin
reg_rdata_next[0] = l1d_insn_commit_qs;
reg_rdata_next[0] = l1d_spm_commit_qs;
end

addr_hit[17]: begin
reg_rdata_next[0] = l1d_insn_commit_qs;
end

addr_hit[18]: begin
reg_rdata_next[0] = l1d_flush_status_qs;
end

Expand Down
Binary file modified hw/system/spatz_cluster/test/bootrom.bin
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