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ci: Fix some Verible warnings
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@suehtamacv
suehtamacv committed Sep 18, 2023
1 parent dcad1f5 commit 33411e5
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Showing 13 changed files with 142 additions and 128 deletions.
10 changes: 9 additions & 1 deletion .github/verible.waiver
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Expand Up @@ -2,5 +2,13 @@
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0

# Auto-generated configuration registers are waived
waive --rule=typedef-structs-unions --location="hw/system/spatz_cluster/src/spatz_cluster_peripheral/*"
waive --rule=line-length --location="hw/system/spatz_cluster/src/spatz_cluster_peripheral/*"
waive --rule=no-trailing-spaces --location="hw/system/spatz_cluster/src/spatz_cluster_peripheral/*"
waive --rule=parameter-name-style --location="hw/system/spatz_cluster/src/spatz_cluster_peripheral/*"
# Our parameters are not CamelCase
waive --rule=parameter-name-style --location="hw/ip/snitch/src/snitch_pkg.sv"
waive --rule=parameter-name-style --location="hw/ip/spatz/src/spatz_pkg.sv"
# We have some long lines
waive --rule=line-length --location="hw/*"
waive --rule=line-length --location="hw/*"
1 change: 1 addition & 0 deletions .github/workflows/ci.yml
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Expand Up @@ -55,3 +55,4 @@ jobs:
domain: iis-git.ee.ethz.ch
repo: github-mirror/spatz
token: ${{ secrets.GITLAB_TOKEN }}
poll-count: 2160
2 changes: 1 addition & 1 deletion hw/ip/spatz/src/reorder_buffer.sv
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Expand Up @@ -15,7 +15,7 @@ module reorder_buffer
parameter int unsigned NumWords = 0,
parameter bit FallThrough = 1'b0,
// Dependant parameters. Do not change!
parameter IdWidth = idx_width(NumWords),
parameter int unsigned IdWidth = idx_width(NumWords),
parameter type data_t = logic [DataWidth-1:0],
parameter type id_t = logic [IdWidth-1:0]
) (
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19 changes: 11 additions & 8 deletions hw/ip/spatz/src/spatz_fpu_sequencer.sv
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Expand Up @@ -158,12 +158,13 @@ module spatz_fpu_sequencer
// Instruction decoder //
///////////////////////////

enum logic [1:0] {
typedef enum logic [1:0] {
Byte = 2'b00,
HalfWord = 2'b01,
Word = 2'b10,
Double = 2'b11
} ls_size;
} ls_size_t;
ls_size_t ls_size;

always_comb begin
// We are not reading any operands
Expand Down Expand Up @@ -380,10 +381,11 @@ module spatz_fpu_sequencer
riscv_instr::FLD: begin
use_fd = 1'b1;
casez (issue_req_i.data_op)
riscv_instr::FLB: ls_size = Byte;
riscv_instr::FLH: ls_size = HalfWord;
riscv_instr::FLW: ls_size = Word;
riscv_instr::FLB: ls_size = Byte;
riscv_instr::FLH: ls_size = HalfWord;
riscv_instr::FLW: ls_size = Word;
riscv_instr::FLD: if (RVD) ls_size = Double;
default:;
endcase
is_load = 1'b1;
illegal_inst = !RVD && issue_req_i.data_op inside {riscv_instr::FLD};
Expand All @@ -394,10 +396,11 @@ module spatz_fpu_sequencer
riscv_instr::FSD: begin
use_fs2 = 1'b1;
casez (issue_req_i.data_op)
riscv_instr::FSB: ls_size = Byte;
riscv_instr::FSH: ls_size = HalfWord;
riscv_instr::FSW: ls_size = Word;
riscv_instr::FSB: ls_size = Byte;
riscv_instr::FSH: ls_size = HalfWord;
riscv_instr::FSW: ls_size = Word;
riscv_instr::FSD: if (RVD) ls_size = Double;
default:;
endcase
is_store = 1'b1;
illegal_inst = !RVD && issue_req_i.data_op inside {riscv_instr::FSD};
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58 changes: 34 additions & 24 deletions hw/ip/spatz/src/spatz_ipu.sv
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Expand Up @@ -108,13 +108,15 @@ module spatz_ipu import spatz_pkg::*; import rvv_pkg::vew_e; #(

if (MAXEW == rvv_pkg::EW_32) begin: gen_32b_ipu

struct packed {
typedef struct packed {
logic [1:0][7:0] ew8;
logic [15:0] ew16;
logic [31:0] ew32;
} input_ops_t;

typedef struct packed {
// Input operands
struct packed {
logic [1:0][7:0] ew8;
logic [15:0] ew16;
logic [31:0] ew32;
} [2:0] ops;
input_ops_t [2:0] ops;
// Input carry
logic [1:0] ew8_carry;
logic ew16_carry;
Expand All @@ -123,21 +125,25 @@ module spatz_ipu import spatz_pkg::*; import rvv_pkg::vew_e; #(
logic [1:0] ew8_valid;
logic ew16_valid;
logic ew32_valid;
} lane_signal_inp;
} lane_signal_inp_t;

lane_signal_inp_t lane_signal_inp;

// SIMD output signals
struct packed {
typedef struct packed {
// Results
logic [1:0][7:0] ew8_res;
logic [15:0] ew16_res;
logic [31:0] ew32_res;
} lane_signal_res;
} lane_signal_res_t;
lane_signal_res_t lane_signal_res;

struct packed {
typedef struct packed {
logic [1:0] ew8_valid;
logic ew16_valid;
logic ew32_valid;
} lane_signal_res_valid;
} lane_signal_res_valid_t;
lane_signal_res_valid_t lane_signal_res_valid;

/////////////////
// Distributor //
Expand Down Expand Up @@ -310,15 +316,16 @@ module spatz_ipu import spatz_pkg::*; import rvv_pkg::vew_e; #(
);

end: gen_32b_ipu else if (MAXEW == rvv_pkg::EW_64) begin: gen_64b_ipu

struct packed {
typedef struct packed {
logic [3:0][7:0] ew8;
logic [1:0][15:0] ew16;
logic [31:0] ew32;
logic [63:0] ew64;
} input_ops_t;

typedef struct packed {
// Input operands
struct packed {
logic [3:0][7:0] ew8;
logic [1:0][15:0] ew16;
logic [31:0] ew32;
logic [63:0] ew64;
} [2:0] ops;
input_ops_t [2:0] ops;
// Input carry
logic [3:0] ew8_carry;
logic [1:0] ew16_carry;
Expand All @@ -329,23 +336,26 @@ module spatz_ipu import spatz_pkg::*; import rvv_pkg::vew_e; #(
logic [1:0] ew16_valid;
logic ew32_valid;
logic ew64_valid;
} lane_signal_inp;
} lane_signal_inp_t;
lane_signal_inp_t lane_signal_inp;

// SIMD output signals
struct packed {
typedef struct packed {
// Results
logic [3:0][7:0] ew8_res;
logic [1:0][15:0] ew16_res;
logic [31:0] ew32_res;
logic [63:0] ew64_res;
} lane_signal_res;
} lane_signal_res_t;
lane_signal_res_t lane_signal_res;

struct packed {
typedef struct packed {
logic [3:0] ew8_valid;
logic [1:0] ew16_valid;
logic ew32_valid;
logic ew64_valid;
} lane_signal_res_valid;
} lane_signal_res_valid_t;
lane_signal_res_valid_t lane_signal_res_valid;

/////////////////
// Distributor //
Expand Down
7 changes: 4 additions & 3 deletions hw/ip/spatz/src/spatz_serdiv.sv
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Expand Up @@ -10,7 +10,7 @@
// Based on Ariane Multiply Divide

module spatz_serdiv #(
parameter WIDTH = 64,
parameter int unsigned WIDTH = 64,
parameter int unsigned IdWidth = 5
) (
input logic clk_i,
Expand Down Expand Up @@ -48,9 +48,10 @@ module spatz_serdiv #(
rem = 1'b1;
end

enum logic [1:0] {
typedef enum logic [1:0] {
IDLE, DIVIDE, FINISH
} state_d, state_q;
} state_t;
state_t state_d, state_q;

logic [WIDTH-1:0] res_q, res_d;
logic [WIDTH-1:0] op_a_q, op_a_d;
Expand Down
18 changes: 9 additions & 9 deletions hw/ip/spatz/src/spatz_simd_lane.sv
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Expand Up @@ -101,8 +101,8 @@ module spatz_simd_lane import spatz_pkg::*; import rvv_pkg::vew_e; #(

logic [$clog2(Width)-1:0] shift_amount;
logic [Width-1:0] shift_operand;
if (Width >= 64) begin : shift_operands
always_comb begin : shift_operands
if (Width >= 64) begin : gen_shift_operands_64
always_comb begin
unique case (sew_i)
rvv_pkg::EW_64: begin
shift_amount = op_s1_i[5:0];
Expand All @@ -124,9 +124,9 @@ module spatz_simd_lane import spatz_pkg::*; import rvv_pkg::vew_e; #(
else shift_operand = $unsigned(op_s2_i[7:0]);
end
endcase
end
end else if (Width >= 32) begin
always_comb begin : shift_operands
end // always_comb
end else if (Width >= 32) begin: gen_shift_operands_32
always_comb begin
unique case (sew_i)
rvv_pkg::EW_32: begin
shift_amount = op_s1_i[4:0];
Expand All @@ -143,9 +143,9 @@ module spatz_simd_lane import spatz_pkg::*; import rvv_pkg::vew_e; #(
else shift_operand = $unsigned(op_s2_i[7:0]);
end
endcase
end // shift_operands
end else if (Width >= 16) begin
always_comb begin : shift_operands
end // always_comb
end else if (Width >= 16) begin: gen_shift_operands_16
always_comb begin
unique case (sew_i)
rvv_pkg::EW_16: begin
shift_amount = op_s1_i[3:0];
Expand All @@ -158,7 +158,7 @@ module spatz_simd_lane import spatz_pkg::*; import rvv_pkg::vew_e; #(
end
endcase
end // shift_operands
end else begin
end else begin: gen_shift_operands_8
always_comb begin
shift_amount = op_s1_i[2:0];
shift_operand = op_s2_i[7:0];
Expand Down
31 changes: 16 additions & 15 deletions hw/ip/spatz/src/spatz_vfu.sv
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Expand Up @@ -103,9 +103,10 @@ module spatz_vfu
assign nr_elem_word = (N_FU * (1 << (MAXEW - spatz_req.vtype.vsew))) >> spatz_req.op_arith.is_narrowing;

// Are we running integer or floating-point instructions?
enum logic {
typedef enum logic {
VFU_RunningIPU, VFU_RunningFPU
} state_d, state_q;
} state_t;
state_t state_d, state_q;
`FF(state_q, state_d, VFU_RunningFPU)

// Propagate the tags through the functional units
Expand Down Expand Up @@ -163,13 +164,14 @@ module spatz_vfu
logic last_request;

// Reduction state
enum logic [2:0] {
typedef enum logic [2:0] {
Reduction_NormalExecution,
Reduction_Wait,
Reduction_Init,
Reduction_Reduce,
Reduction_WriteBack
} reduction_state_d, reduction_state_q;
} reduction_state_t;
reduction_state_t reduction_state_d, reduction_state_q;
`FF(reduction_state_q, reduction_state_d, Reduction_NormalExecution)

// Is the reduction done?
Expand Down Expand Up @@ -242,6 +244,7 @@ module spatz_vfu
stall = 1'b1;
end
end
default:;
endcase

// Finished the execution!
Expand Down Expand Up @@ -668,6 +671,7 @@ module spatz_vfu
ipu_wide_operand2[16*el +: 16] = spatz_req.op_arith.signed_vs2 ? {{8{shift_operand2[8*el+7]}}, shift_operand2[8*el +: 8]} : {8'b0, shift_operand2[8*el +: 8]};
end
end
default:;
endcase
end: gen_ipu_widening

Expand Down Expand Up @@ -733,7 +737,7 @@ module spatz_vfu
assign ipu_result = ipu_result_q;
assign ipu_result_valid = ipu_result_valid_q;
assign ipu_result_tag = ipu_result_tag_q;
end: gen_pipeline_ipu else begin
end: gen_pipeline_ipu else begin: gen_no_pipeline_ipu
assign ipu_in_ready = int_ipu_in_ready;
assign int_ipu_operand1 = ipu_wide_operand1;
assign int_ipu_operand2 = ipu_wide_operand2;
Expand Down Expand Up @@ -824,19 +828,15 @@ module spatz_vfu
fpu_vectorial_op = FLEN > 32;
end
EW_16: begin
fpu_src_fmt = spatz_req.op_arith.is_narrowing || spatz_req.op_arith.widen_vs1 || spatz_req.op_arith.widen_vs2 ? fpnew_pkg::FP32 :
spatz_req.fm.src ? fpnew_pkg::FP16ALT : fpnew_pkg::FP16;
fpu_dst_fmt = spatz_req.op_arith.widen_vs1 || spatz_req.op_arith.widen_vs2 || spatz_req.op == VSDOTP ? fpnew_pkg::FP32 :
spatz_req.fm.dst ? fpnew_pkg::FP16ALT : fpnew_pkg::FP16;
fpu_int_fmt = spatz_req.op_arith.is_narrowing && spatz_req.op inside {VI2F, VU2F} ? fpnew_pkg::INT32 : fpnew_pkg::INT16;
fpu_src_fmt = spatz_req.op_arith.is_narrowing || spatz_req.op_arith.widen_vs1 || spatz_req.op_arith.widen_vs2 ? fpnew_pkg::FP32 : (spatz_req.fm.src ? fpnew_pkg::FP16ALT : fpnew_pkg::FP16);
fpu_dst_fmt = spatz_req.op_arith.widen_vs1 || spatz_req.op_arith.widen_vs2 || spatz_req.op == VSDOTP ? fpnew_pkg::FP32 : (spatz_req.fm.dst ? fpnew_pkg::FP16ALT : fpnew_pkg::FP16);
fpu_int_fmt = spatz_req.op_arith.is_narrowing && spatz_req.op inside {VI2F, VU2F} ? fpnew_pkg::INT32 : fpnew_pkg::INT16;
fpu_vectorial_op = 1'b1;
end
EW_8: begin
fpu_src_fmt = spatz_req.op_arith.is_narrowing || spatz_req.op_arith.widen_vs1 || spatz_req.op_arith.widen_vs2 ? spatz_req.fm.src ? fpnew_pkg::FP16ALT : fpnew_pkg::FP16 :
spatz_req.fm.src ? fpnew_pkg::FP8ALT : fpnew_pkg::FP8;
fpu_dst_fmt = spatz_req.op_arith.widen_vs1 || spatz_req.op_arith.widen_vs2 || spatz_req.op == VSDOTP ? spatz_req.fm.dst ? fpnew_pkg::FP16ALT : fpnew_pkg::FP16 :
spatz_req.fm.dst ? fpnew_pkg::FP8ALT : fpnew_pkg::FP8;
fpu_int_fmt = spatz_req.op_arith.is_narrowing && spatz_req.op inside {VI2F, VU2F} ? fpnew_pkg::INT16 : fpnew_pkg::INT8;
fpu_src_fmt = spatz_req.op_arith.is_narrowing || spatz_req.op_arith.widen_vs1 || spatz_req.op_arith.widen_vs2 ? (spatz_req.fm.src ? fpnew_pkg::FP16ALT : fpnew_pkg::FP16) : (spatz_req.fm.src ? fpnew_pkg::FP8ALT : fpnew_pkg::FP8);
fpu_dst_fmt = spatz_req.op_arith.widen_vs1 || spatz_req.op_arith.widen_vs2 || spatz_req.op == VSDOTP ? (spatz_req.fm.dst ? fpnew_pkg::FP16ALT : fpnew_pkg::FP16) : (spatz_req.fm.dst ? fpnew_pkg::FP8ALT : fpnew_pkg::FP8);
fpu_int_fmt = spatz_req.op_arith.is_narrowing && spatz_req.op inside {VI2F, VU2F} ? fpnew_pkg::INT16 : fpnew_pkg::INT8;
fpu_vectorial_op = 1'b1;
end
default:;
Expand Down Expand Up @@ -935,6 +935,7 @@ module spatz_vfu
wide_operand2[16*el +: 16] = widen_fp8_to_fp16(shift_operand2[8*el +: 8]);
end
end
default:;
endcase
end: gen_widening

Expand Down
15 changes: 10 additions & 5 deletions hw/ip/spatz/src/spatz_vsldu.sv
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Expand Up @@ -160,10 +160,11 @@ module spatz_vsldu
`FF(running_q, running_d, '0)

// Respond to controller if we are finished executing
enum logic {
typedef enum logic {
VSLDU_RUNNING, // Running an instruction
VSLDU_WAIT_WVALID // Waiting for the last wvalid to acknowledge the instruction
} state_q, state_d;
} state_t;
state_t state_q, state_d;
`FF(state_q, state_d, VSLDU_RUNNING)

// New instruction
Expand Down Expand Up @@ -223,10 +224,11 @@ module spatz_vsldu
logic vreg_operation_last;

// FSM to decide whether we are on the first operation or not
enum logic {
typedef enum logic {
VREG_IDLE,
VREG_WAIT_FIRST_WRITE
} vreg_operation_first_q, vreg_operation_first_d;
} vreg_operation_first_t;
vreg_operation_first_t vreg_operation_first_q, vreg_operation_first_d;
`FF(vreg_operation_first_q, vreg_operation_first_d, VREG_IDLE)

always_comb begin: vsldu_vreg_counter_proc
Expand Down Expand Up @@ -263,6 +265,7 @@ module spatz_vsldu
if (vrf_req_valid_d && vrf_req_ready_d)
vreg_operation_first_d = VREG_IDLE;
end
default:;
endcase
vreg_operation_last = spatz_req_valid && !prefetch_q && (delta <= (VRFWordBWidth - vreg_counter_q[idx_width(VRFWordBWidth)-1:0]));

Expand Down Expand Up @@ -326,7 +329,9 @@ module spatz_vsldu
state_d = VSLDU_WAIT_WVALID;
end
end
end
end // case: VSLDU_WAIT_WVALID

default:;
endcase
end: vsldu_rsp

Expand Down
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