hw: Fully gate debug support in Snitch core
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GitHub Actions / verible-verilog-lint
failed
Sep 27, 2023 in 1s
reviewdog [verible-verilog-lint] report
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Findings (1)
hw/snitch/src/snitch.sv|493 col 101| Line length exceeds max: 100; is: 109 [Style: line-length] [line-length]
Filtered Findings (0)
Annotations
Check warning on line 493 in hw/snitch/src/snitch.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/snitch/src/snitch.sv#L493
Line length exceeds max: 100; is: 109 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 109 [Style: line-length] [line-length]" location:{path:"./hw/snitch/src/snitch.sv" range:{start:{line:493 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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