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use_c2c_tiles to params.hjson, remove legacy gemm_baseline
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rogerbarton committed Feb 9, 2024
1 parent c056eac commit e37ba95
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Showing 7 changed files with 40 additions and 192 deletions.
1 change: 1 addition & 0 deletions sw/blas/gemm/data/datagen.py
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Expand Up @@ -122,6 +122,7 @@ def emit_header(**kwargs):
# gemmImpl
data_str += ["// -- gemmImpl"]
data_str += [f"#define USE_METHOD {gemmImpl['method']}"]
data_str += [f"#define USE_C2C_TILES {int(gemmImpl['use_c2c_tiles'])}"]
data_str += [f"#define L1_M {gemmImpl['L1_M']}"]
data_str += [f"#define L1_N {gemmImpl['L1_N']}"]
data_str += [f"#define L1_K {gemmImpl['L1_K']}"]
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11 changes: 6 additions & 5 deletions sw/blas/gemm/data/params.hjson
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Expand Up @@ -21,11 +21,12 @@
}

gemmImpl: {
method: "baseline",
L1_M: 8,
L1_N: 8,
L1_K: 8,
ta_tile: false,
method: "2dpipe",
use_c2c_tiles: true,
L1_M: 16,
L1_N: 16,
L1_K: 16,
ta_tile: true,
tb_tile: false,
tc_tile: false, // not implemented
expand: 0,
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6 changes: 6 additions & 0 deletions sw/blas/gemm/src/dma_xfer_test.h
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@@ -1,5 +1,11 @@
#include "gemm_decls.h"

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/**
* Test DMA effective bandwidth.
* Transfers an array from HBM to TCDM,
* then rotates between cluster TCDMs with C2C communication,
* then stores the result back to HBM.
*/
void dma_xfer_test(const double* A, const uint32_t N, const bool bench) {
if (!snrt_is_dm_core()) return;

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183 changes: 0 additions & 183 deletions sw/blas/gemm/src/gemm_baseline.h

This file was deleted.

27 changes: 27 additions & 0 deletions sw/blas/gemm/src/gemm_kernel_legacy.h
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Expand Up @@ -23,6 +23,33 @@ typedef __fp16 v4f16 __attribute__((vector_size(8)));
typedef char v8f8 __attribute__((vector_size(8)));
#endif

/**
* \brief Each cluster performs a GEMM for A, B, C inside each TCDM
*/
void gemm_cluster_kernel_baseline(double alpha, double beta, uint32_t M, uint32_t N,
uint32_t K, double* const A, double* const B,
double* const C, int lda, int ldb, int ldc) {
uint32_t p[3], P[3];
ocrt_thread_idx(p);
ocrt_compute_thread_num(P);

for (uint32_t i = p[0]; i < M; i += P[0]) {
for (uint32_t j = 0; j < N; j++) {
uint32_t cIdx = i * ldc + j; // C[i][j]
register double c0 = beta * C[cIdx];

for (uint32_t k = 0; k < K; k++) {
uint32_t aIdx = i * lda + k; // A[i][k]
uint32_t bIdx = k * ldb + j; // B[k][j]

c0 += A[aIdx] * B[bIdx];
}
C[cIdx] = c0;
}
}
snrt_fpu_fence();
}

void gemm_fp64_baseline(uint32_t M, uint32_t N, uint32_t K, double* A,
uint32_t ldA, uint32_t ta, double* B, uint32_t ldB,
uint32_t tb, double* C, uint32_t ldC, double ALPHA) {
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2 changes: 0 additions & 2 deletions sw/blas/gemm/src/gemm_tiling_2dpipe_tpl.h
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Expand Up @@ -10,8 +10,6 @@

void SNBLAS_GEMM_TILING(2dpipe, FLOAT_T, IS_DM_CORE) (const SnblasGemmInfo info, const SNBLAS_GEMM_ARGS(FLOAT_T) args, const SnblasGemmImpl impl) {

#define USE_C2C_TILES true

/**
* Problem is double buffered in L1. The buffer that is used is toggled at
* each iteration. The DMA cores are one index step ahead so they load the
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2 changes: 0 additions & 2 deletions sw/blas/gemm/src/main.c
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Expand Up @@ -21,8 +21,6 @@
NAMED_DUMP(uint32_t, err, 0x7)
NAMED_DUMP(uint32_t, bench_iter, 0x7)

#define BIST
#include "data.h"

int main() {
const bool setup_ssr = true;
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