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Use CamelCase parameters in snitch_regfile
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@fischeti
fischeti committed Jul 3, 2024
1 parent 8a105b1 commit c619022
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Showing 6 changed files with 88 additions and 88 deletions.
10 changes: 5 additions & 5 deletions hw/snitch/src/snitch.sv
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Expand Up @@ -2623,11 +2623,11 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
// pragma translate_on

snitch_regfile #(
.DATA_WIDTH ( 32 ),
.NR_READ_PORTS ( 2 ),
.NR_WRITE_PORTS ( 1 ),
.ZERO_REG_ZERO ( 1 ),
.ADDR_WIDTH ( RegWidth )
.DataWidth ( 32 ),
.NrReadPorts ( 2 ),
.NrWritePorts ( 1 ),
.ZeroRegZero ( 1 ),
.AddrWidth ( RegWidth )
) i_snitch_regfile (
.clk_i,
.rst_ni ( ~rst_i ),
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48 changes: 24 additions & 24 deletions hw/snitch/src/snitch_regfile_ff.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -6,42 +6,42 @@
// Description: Variable Register File
// verilog_lint: waive module-filename
module snitch_regfile #(
parameter int unsigned DATA_WIDTH = 32,
parameter int unsigned NR_READ_PORTS = 2,
parameter int unsigned NR_WRITE_PORTS = 1,
parameter bit ZERO_REG_ZERO = 0,
parameter int unsigned ADDR_WIDTH = 4
parameter int unsigned DataWidth = 32,
parameter int unsigned NrReadPorts = 2,
parameter int unsigned NrWritePorts = 1,
parameter bit ZeroRegZero = 0,
parameter int unsigned AddrWidth = 4
) (
// clock and reset
input logic clk_i,
input logic rst_ni,
input logic clk_i,
input logic rst_ni,
// read port
input logic [NR_READ_PORTS-1:0][ADDR_WIDTH-1:0] raddr_i,
output logic [NR_READ_PORTS-1:0][DATA_WIDTH-1:0] rdata_o,
input logic [NrReadPorts-1:0][AddrWidth-1:0] raddr_i,
output logic [NrReadPorts-1:0][DataWidth-1:0] rdata_o,
// write port
input logic [NR_WRITE_PORTS-1:0][ADDR_WIDTH-1:0] waddr_i,
input logic [NR_WRITE_PORTS-1:0][DATA_WIDTH-1:0] wdata_i,
input logic [NR_WRITE_PORTS-1:0] we_i
input logic [NrWritePorts-1:0][AddrWidth-1:0] waddr_i,
input logic [NrWritePorts-1:0][DataWidth-1:0] wdata_i,
input logic [NrWritePorts-1:0] we_i
);

localparam int unsigned NumWords = 2**ADDR_WIDTH;
localparam int unsigned NumWords = 2**AddrWidth;

logic [NumWords-1:0][DATA_WIDTH-1:0] mem;
logic [NR_WRITE_PORTS-1:0][NumWords-1:0] we_dec;
logic [NumWords-1:0][DataWidth-1:0] mem;
logic [NrWritePorts-1:0][NumWords-1:0] we_dec;


always_comb begin : we_decoder
for (int unsigned j = 0; j < NR_WRITE_PORTS; j++) begin
for (int unsigned i = 0; i < NumWords; i++) begin
if (waddr_i[j] == i) we_dec[j][i] = we_i[j];
else we_dec[j][i] = 1'b0;
end
always_comb begin : we_decoder
for (int unsigned j = 0; j < NrWritePorts; j++) begin
for (int unsigned i = 0; i < NumWords; i++) begin
if (waddr_i[j] == i) we_dec[j][i] = we_i[j];
else we_dec[j][i] = 1'b0;
end
end
end

// loop from 1 to NumWords-1 as R0 is nil
always_ff @(posedge clk_i, negedge rst_ni) begin : register_write_behavioral
for (int unsigned j = 0; j < NR_WRITE_PORTS; j++) begin
for (int unsigned j = 0; j < NrWritePorts; j++) begin
for (int unsigned i = 0; i < NumWords; i++) begin
if (~rst_ni) begin
mem[i] <= '0;
Expand All @@ -51,13 +51,13 @@ module snitch_regfile #(
end
end
end
if (ZERO_REG_ZERO) begin
if (ZeroRegZero) begin
mem[0] <= '0;
end
end
end

for (genvar i = 0; i < NR_READ_PORTS; i++) begin : gen_read_port
for (genvar i = 0; i < NrReadPorts; i++) begin : gen_read_port
assign rdata_o[i] = mem[raddr_i[i]];
end

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48 changes: 24 additions & 24 deletions hw/snitch/src/snitch_regfile_fpga.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -22,42 +22,42 @@

// verilog_lint: waive module-filename
module snitch_regfile #(
parameter int unsigned DATA_WIDTH = 32,
parameter int unsigned NR_READ_PORTS = 2,
parameter int unsigned NR_WRITE_PORTS = 1,
parameter bit ZERO_REG_ZERO = 0,
parameter int unsigned ADDR_WIDTH = 4
parameter int unsigned DataWidth = 32,
parameter int unsigned NrReadPorts = 2,
parameter int unsigned NrWritePorts = 1,
parameter bit ZeroRegZero = 0,
parameter int unsigned AddrWidth = 4
)(
// clock and reset
input logic clk_i,
input logic rst_ni,
input logic clk_i,
input logic rst_ni,
// read port
input logic [NR_READ_PORTS-1:0][4:0] raddr_i,
output logic [NR_READ_PORTS-1:0][DATA_WIDTH-1:0] rdata_o,
input logic [NrReadPorts-1:0][4:0] raddr_i,
output logic [NrReadPorts-1:0][DataWidth-1:0] rdata_o,
// write port
input logic [NR_WRITE_PORTS-1:0][4:0] waddr_i,
input logic [NR_WRITE_PORTS-1:0][DATA_WIDTH-1:0] wdata_i,
input logic [NR_WRITE_PORTS-1:0] we_i
input logic [NrWritePorts-1:0][4:0] waddr_i,
input logic [NrWritePorts-1:0][DataWidth-1:0] wdata_i,
input logic [NrWritePorts-1:0] we_i
);

localparam int unsigned NumWords = 2**ADDR_WIDTH;
localparam int unsigned LogNrWritePorts = NR_WRITE_PORTS == 1 ? 1 : $clog2(NR_WRITE_PORTS);
localparam int unsigned NumWords = 2**AddrWidth;
localparam int unsigned LogNrWritePorts = NrWritePorts == 1 ? 1 : $clog2(NrWritePorts);

// The register values are stored in distinct separate RAM blocks each featuring 1 sync-write and
// N async-read ports. A set of narrow flip-flops keeps track of which RAM block contains the
// valid entry for each register.

// Distributed RAM usually supports one write port per block. We need one block per write port.
logic [NumWords-1:0][DATA_WIDTH-1:0] mem [NR_WRITE_PORTS];
logic [NumWords-1:0][DataWidth-1:0] mem [NrWritePorts];


logic [NR_WRITE_PORTS-1:0][NumWords-1:0] we_dec;
logic [NrWritePorts-1:0][NumWords-1:0] we_dec;
logic [NumWords-1:0][LogNrWritePorts-1:0] mem_block_sel;
logic [NumWords-1:0][LogNrWritePorts-1:0] mem_block_sel_q;

// write adress decoder (for block selector)
always_comb begin
for (int unsigned j = 0; j < NR_WRITE_PORTS; j++) begin
for (int unsigned j = 0; j < NrWritePorts; j++) begin
for (int unsigned i = 0; i < NumWords; i++) begin
if (waddr_i[j] == i) begin
we_dec[j][i] = we_i[j];
Expand All @@ -75,7 +75,7 @@ module snitch_regfile #(
always_comb begin
mem_block_sel = mem_block_sel_q;
for (int i = 0; i<NumWords; i++) begin
for (int j = 0; j<NR_WRITE_PORTS; j++) begin
for (int j = 0; j<NrWritePorts; j++) begin
if (we_dec[j][i] == 1'b1) begin
mem_block_sel[i] = LogNrWritePorts'(j);
end
Expand All @@ -87,20 +87,20 @@ module snitch_regfile #(
`FF(mem_block_sel_q, mem_block_sel, '0, clk_i, rst_ni)

// distributed RAM blocks
logic [NR_READ_PORTS-1:0] [DATA_WIDTH-1:0] mem_read [NR_WRITE_PORTS];
for (genvar j=0; j<NR_WRITE_PORTS; j++) begin : gen_regfile_ram_block
logic [NrReadPorts-1:0] [DataWidth-1:0] mem_read [NrWritePorts];
for (genvar j=0; j<NrWritePorts; j++) begin : gen_regfile_ram_block
`FFL(mem[j][waddr_i[j]], wdata_i[j], we_i[j], '0, clk_i, rst_ni)
for (genvar k=0; k<NR_READ_PORTS; k++) begin : gen_block_read
for (genvar k=0; k<NrReadPorts; k++) begin : gen_block_read
assign mem_read[j][k] = mem[j][raddr_i[k]];
end
end

// output MUX
logic [NR_READ_PORTS-1:0][LogNrWritePorts-1:0] block_addr;
for (genvar k = 0; k < NR_READ_PORTS; k++) begin : gen_regfile_read_port
logic [NrReadPorts-1:0][LogNrWritePorts-1:0] block_addr;
for (genvar k = 0; k < NrReadPorts; k++) begin : gen_regfile_read_port
assign block_addr[k] = mem_block_sel_q[raddr_i[k]];
assign rdata_o[k] =
(ZERO_REG_ZERO && raddr_i[k] == '0 ) ? '0 : mem_read[block_addr[k]][k];
(ZeroRegZero && raddr_i[k] == '0 ) ? '0 : mem_read[block_addr[k]][k];
end

endmodule
50 changes: 25 additions & 25 deletions hw/snitch/src/snitch_regfile_latch.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -6,36 +6,36 @@
// Description: Variable Register File
// verilog_lint: waive module-filename
module snitch_regfile #(
parameter int unsigned DATA_WIDTH = 32,
parameter int unsigned NR_READ_PORTS = 2,
parameter int unsigned NR_WRITE_PORTS = 1,
parameter bit ZERO_REG_ZERO = 1,
parameter int unsigned ADDR_WIDTH = 4
parameter int unsigned DataWidth = 32,
parameter int unsigned NrReadPorts = 2,
parameter int unsigned NrWritePorts = 1,
parameter bit ZeroRegZero = 1,
parameter int unsigned AddrWidth = 4
) (
// clock and reset
input logic clk_i,
input logic rst_ni,
input logic clk_i,
input logic rst_ni,
// read port
input logic [NR_READ_PORTS-1:0][ADDR_WIDTH-1:0] raddr_i,
output logic [NR_READ_PORTS-1:0][DATA_WIDTH-1:0] rdata_o,
input logic [NrReadPorts-1:0][AddrWidth-1:0] raddr_i,
output logic [NrReadPorts-1:0][DataWidth-1:0] rdata_o,
// write port
input logic [NR_WRITE_PORTS-1:0][ADDR_WIDTH-1:0] waddr_i,
input logic [NR_WRITE_PORTS-1:0][DATA_WIDTH-1:0] wdata_i,
input logic [NR_WRITE_PORTS-1:0] we_i
input logic [NrWritePorts-1:0][AddrWidth-1:0] waddr_i,
input logic [NrWritePorts-1:0][DataWidth-1:0] wdata_i,
input logic [NrWritePorts-1:0] we_i
);

localparam int unsigned NumWords = 2**ADDR_WIDTH;
localparam int unsigned NumWords = 2**AddrWidth;

logic clk;
logic [NumWords-1:0] mem_clocks;

logic [NumWords-1:0][DATA_WIDTH-1:0] mem;
logic [NumWords-1:0][DataWidth-1:0] mem;

logic [NR_WRITE_PORTS-1:0][DATA_WIDTH-1:0] wdata_q;
logic [NR_WRITE_PORTS-1:0][NumWords-1:0] waddr_onehot;
logic [NumWords-1:0][NR_WRITE_PORTS-1:0] waddr_onehot_trans; // transposed index version
logic [NrWritePorts-1:0][DataWidth-1:0] wdata_q;
logic [NrWritePorts-1:0][NumWords-1:0] waddr_onehot;
logic [NumWords-1:0][NrWritePorts-1:0] waddr_onehot_trans; // transposed index version

for (genvar i = 0; i < NR_WRITE_PORTS; i++) begin : gen_oh_write_ports
for (genvar i = 0; i < NrWritePorts; i++) begin : gen_oh_write_ports
for (genvar j = 0; j < NumWords; j++) begin : gen_oh_words
assign waddr_onehot_trans[j][i] = waddr_onehot[i][j];
end
Expand All @@ -49,11 +49,11 @@ module snitch_regfile #(
);

// Sample Input Data
for (genvar i = 0; i < NR_WRITE_PORTS; i++) begin : gen_data_ports
for (genvar i = 0; i < NrWritePorts; i++) begin : gen_data_ports

`FF(wdata_q[i], wdata_i[i], '0, clk, rst_ni)

for (genvar j = ZERO_REG_ZERO; j < NumWords; j++) begin : gen_data_words
for (genvar j = ZeroRegZero; j < NumWords; j++) begin : gen_data_words
always_comb begin
if (we_i[i] && waddr_i[i] == j) waddr_onehot[i][j] = 1'b1;
else waddr_onehot[i][j] = 1'b0;
Expand All @@ -71,10 +71,10 @@ module snitch_regfile #(
end

always_latch begin
if (ZERO_REG_ZERO) mem[0] = '0;
if (ZeroRegZero) mem[0] = '0;

for (int unsigned i = ZERO_REG_ZERO; i < NumWords; i++) begin : gen_read_words
for (int unsigned j = 0; j < NR_WRITE_PORTS; j++) begin : gen_read_ports
for (int unsigned i = ZeroRegZero; i < NumWords; i++) begin : gen_read_words
for (int unsigned j = 0; j < NrWritePorts; j++) begin : gen_read_ports
if (mem_clocks[i]) begin
// TODO(zarubaf) generalize to more than 1 read port
mem[i] = wdata_q[j];
Expand All @@ -83,6 +83,6 @@ module snitch_regfile #(
end
end

for (genvar i = 0; i < NR_READ_PORTS; i++) assign rdata_o[i] = mem[raddr_i[i][ADDR_WIDTH-1:0]];
for (genvar i = 0; i < NrReadPorts; i++) assign rdata_o[i] = mem[raddr_i[i][AddrWidth-1:0]];

endmodule
10 changes: 5 additions & 5 deletions hw/snitch_cluster/src/snitch_fp_ss.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -2413,11 +2413,11 @@ module snitch_fp_ss import snitch_pkg::*; #(
end

snitch_regfile #(
.DATA_WIDTH ( FLEN ),
.NR_READ_PORTS ( 3 ),
.NR_WRITE_PORTS ( 1 ),
.ZERO_REG_ZERO ( 0 ),
.ADDR_WIDTH ( 5 )
.DataWidth ( FLEN ),
.NrReadPorts ( 3 ),
.NrWritePorts ( 1 ),
.ZeroRegZero ( 0 ),
.AddrWidth ( 5 )
) i_ff_regfile (
.clk_i,
.rst_ni ( ~rst_i ),
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10 changes: 5 additions & 5 deletions hw/snitch_ipu/src/snitch_int_ss.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -608,11 +608,11 @@ module snitch_int_ss import riscv_instr::*; import snitch_ipu_pkg::*; import sni
// Integer Regfile
// ---------------
snitch_regfile #(
.DATA_WIDTH ( 32 ),
.NR_READ_PORTS ( 3 ),
.NR_WRITE_PORTS ( 1 ),
.ZERO_REG_ZERO ( 0 ),
.ADDR_WIDTH ( 5 )
.DataWidth ( 32 ),
.NrReadPorts ( 3 ),
.NrWritePorts ( 1 ),
.ZeroRegZero ( 0 ),
.AddrWidth ( 5 )
) i_ipu_regfile (
.clk_i,
.rst_ni (~rst_i),
Expand Down

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