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target/cluster: Expose cluster_base ports
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fischeti committed Nov 3, 2023
1 parent 8a020de commit bcca6ef
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Showing 3 changed files with 10 additions and 6 deletions.
5 changes: 5 additions & 0 deletions docs/schema/snitch_cluster.schema.json
Original file line number Diff line number Diff line change
Expand Up @@ -141,6 +141,11 @@
"description": "Whether to provide a debug request input and external debug features",
"default": true
},
"cluster_base_expose": {
"type": "boolean",
"description": "Whether to expose base_addr and base_hart_id",
"default": false
},
"sram_cfg_expose": {
"type": "boolean",
"description": "Whether to expose memory cut configuration inputs for implementation",
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10 changes: 5 additions & 5 deletions hw/snitch_cluster/src/snitch_cluster_wrapper.sv.tpl
Original file line number Diff line number Diff line change
Expand Up @@ -222,7 +222,7 @@ module ${cfg['name']}_wrapper (
input logic [${cfg['pkg_name']}::NrCores-1:0] meip_i,
input logic [${cfg['pkg_name']}::NrCores-1:0] mtip_i,
input logic [${cfg['pkg_name']}::NrCores-1:0] msip_i,
% if not cfg['tie_ports']:
% if cfg['cluster_base_expose']:
input logic [9:0] hart_base_id_i,
input logic [${cfg['addr_width']-1}:0] cluster_base_addr_i,
% endif
Expand Down Expand Up @@ -344,12 +344,12 @@ module ${cfg['name']}_wrapper (
.meip_i,
.mtip_i,
.msip_i,
% if cfg['tie_ports']:
.hart_base_id_i (${to_sv_hex(cfg['cluster_base_hartid'], 10)}),
.cluster_base_addr_i (${to_sv_hex(cfg['cluster_base_addr'], cfg['addr_width'])}),
% else:
% if cfg['cluster_base_expose']:
.hart_base_id_i,
.cluster_base_addr_i,
% else:
.hart_base_id_i (${to_sv_hex(cfg['cluster_base_hartid'], 10)}),
.cluster_base_addr_i (${to_sv_hex(cfg['cluster_base_addr'], cfg['addr_width'])}),
% endif
% if cfg['timing']['iso_crossings']:
.clk_d2_bypass_i,
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1 change: 0 additions & 1 deletion util/clustergen/cluster.py
Original file line number Diff line number Diff line change
Expand Up @@ -374,7 +374,6 @@ def __init__(self, cfg):
pma_cfg.add_region_length(PMA.CACHED, self.cfg['dram']['address'],
self.cfg['dram']['length'],
self.cfg['cluster']['addr_width'])
self.cfg['cluster']['tie_ports'] = True
# Store Snitch cluster config in separate variable
self.cluster = SnitchCluster(cfg["cluster"], pma_cfg)

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