target: Align Verilator timescale with Questa

pulp-platform · Jan 12, 2024 · b9af419 · b9af419
1 parent 34764a7
commit b9af419
Showing 1 changed file with 1 addition and 0 deletions.
diff --git a/target/common/common.mk b/target/common/common.mk
@@ -77,6 +77,7 @@ VLT_FLAGS    += -Wno-UNSIGNED
 VLT_FLAGS    += -Wno-UNOPTFLAT
 VLT_FLAGS    += -Wno-fatal
 VLT_FLAGS    += --unroll-count 1024
+VLT_FLAGS    += --timescale 1ns/1ps
 VLT_CFLAGS   += -std=c++14 -pthread
 VLT_CFLAGS   +=-I ${VLT_BUILDDIR} -I $(VLT_ROOT)/include -I $(VLT_ROOT)/include/vltstd -I $(VLT_FESVR)/include -I $(TB_DIR) -I ${MKFILE_DIR}/test