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target: Align Verilator timescale with Questa
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@colluca
colluca committed Aug 9, 2024
1 parent de5053e commit 994973a
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1 change: 1 addition & 0 deletions target/common/common.mk
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Expand Up @@ -79,6 +79,7 @@ VLT_SOURCES = $(shell ${BENDER} script flist ${VLT_BENDER} | ${SED_SRCS})
VLT_BUILDDIR := $(abspath work-vlt)
VLT_FESVR = $(VLT_BUILDDIR)/riscv-isa-sim
VLT_FLAGS += --timing
VLT_FLAGS += --timescale 1ns/1ps
VLT_FLAGS += -Wno-BLKANDNBLK
VLT_FLAGS += -Wno-LITENDIAN
VLT_FLAGS += -Wno-CASEINCOMPLETE
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