hw: Clean up snitch_regfile_ff

hw/snitch/src/snitch_regfile_ff.sv

@@ -3,6 +3,9 @@
 // SPDX-License-Identifier: SHL-0.51
 
 // Author: Florian Zaruba <[email protected]>
+
+`include "common_cells/registers.svh"
+
 // Description: Variable Register File
 // verilog_lint: waive module-filename
 module snitch_regfile #(
@@ -30,29 +33,13 @@ module snitch_regfile #(
   logic [NR_WRITE_PORTS-1:0][NumWords-1:0] we_dec;
 
 
-    always_comb begin : we_decoder
-      for (int unsigned j = 0; j < NR_WRITE_PORTS; j++) begin
-        for (int unsigned i = 0; i < NumWords; i++) begin
-          if (waddr_i[j] == i) we_dec[j][i] = we_i[j];
-          else we_dec[j][i] = 1'b0;
-        end
-      end
-    end
-
-  // loop from 1 to NumWords-1 as R0 is nil
-  always_ff @(posedge clk_i, negedge rst_ni) begin : register_write_behavioral
-    for (int unsigned j = 0; j < NR_WRITE_PORTS; j++) begin
-      for (int unsigned i = 0; i < NumWords; i++) begin
-        if (~rst_ni) begin
-          mem[i] <= '0;
-        end else begin
-          if (we_dec[j][i]) begin
-            mem[i] <= wdata_i[j];
-          end
-        end
-      end
-      if (ZERO_REG_ZERO) begin
-        mem[0] <= '0;
+  for (genvar j = 0; j < NR_WRITE_PORTS; j++) begin : gen_write_port
+    for (genvar i = 0; i < NumWords; i++) begin : gen_we_dec
+      assign we_dec[j][i] = (i == waddr_i[j]) ? we_i[j] : 1'b0;
+      if (i == 0 && ZERO_REG_ZERO) begin
+        assign mem[0] = '0;
+      end else begin
+        `FFL(mem[i], wdata[i], we_dec[j][i], '0, clk_i, rst_ni)
       end
     end
   end