sw: Add alias cluster region test

sw/tests/alias.c

@@ -0,0 +1,46 @@
+// Copyright 2023 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#include "snrt.h"
+
+uint32_t cluster_global_to_local_address(uint32_t global_addr) {
+    return global_addr - snrt_l1_start_addr() + ALIAS_TCDM_BASE_ADDR;
+}
+
+const uint32_t n_inputs = 16;
+volatile int errors = 2 * n_inputs;
+
+int main() {
+    // Get global and local memory aliases
+    volatile uint32_t *buffer_global = snrt_l1_next();
+    volatile uint32_t *buffer_local =
+        (uint32_t *)cluster_global_to_local_address((uint32_t)buffer_global);
+
+    // Test narrow cluster XBAR
+    if (snrt_cluster_core_idx() == 0) {
+        // Write to global buffer
+        for (uint32_t i = 0; i < n_inputs; i++) buffer_global[i] = i;
+        // Read from local buffer
+        for (uint32_t i = 0; i < n_inputs; i++)
+            if (buffer_local[i] == i) errors--;
+    }
+
+    snrt_cluster_hw_barrier();
+
+    // Test wide DMA XBAR
+    if (snrt_is_dm_core()) {
+        // Read from local buffer using DMA
+        buffer_global += n_inputs;
+        snrt_dma_start_1d((void *)buffer_global, (void *)buffer_local,
+                          n_inputs * sizeof(uint32_t));
+        snrt_dma_wait_all();
+        // Check results
+        for (uint32_t i = 0; i < n_inputs; i++)
+            if (buffer_global[i] == i) errors--;
+    }
+
+    snrt_cluster_hw_barrier();
+
+    return errors;
+}

target/snitch_cluster/sw/run.yaml

@@ -3,6 +3,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 runs:
+  - elf: tests/build/alias.elf
   - elf: tests/build/atomics.elf
     simulators: [vsim, vcs, verilator] # banshee fails with exit code 0x4
   - elf: tests/build/barrier.elf

target/snitch_cluster/sw/runtime/common/snitch_cluster_addrmap.h.tpl

@@ -7,3 +7,6 @@
 #define CLUSTER_ZERO_MEM_START_ADDR (CLUSTER_PERIPH_BASE_ADDR + ${hex(cfg['cluster']['cluster_periph_size'] * 1024)})
 #define CLUSTER_ZERO_MEM_END_ADDR (CLUSTER_ZERO_MEM_START_ADDR + ${hex(cfg['cluster']['zero_mem_size'] * 1024)})
 #define CLINT_BASE_ADDR ${hex(cfg['peripherals']['clint']['address'])}
+#define ALIAS_TCDM_BASE_ADDR ${hex(cfg['cluster']['alias_region_base'])}
+#define ALIAS_PERIPH_BASE_ADDR (ALIAS_TCDM_BASE_ADDR + ${hex(cfg['cluster']['tcdm']['size'] * 1024)})
+#define ALIAS_ZERO_MEM_START_ADDR (ALIAS_PERIPH_BASE_ADDR + ${hex(cfg['cluster']['cluster_periph_size'] * 1024)})