Merge remote-tracking branch 'origin/main' into rbarton/gemm

.github/CODEOWNERS

@@ -2,7 +2,7 @@
 # Unless a later match takes precedence, global owners below will be
 # requested for review when someone opens a pull request.
 
-* @paulsc96 @colluca
+* @paulsc96 @colluca @fischeti
 
 hw/snitch_cluster @paulsc96 @lucabertaccini
 hw/snitch_dma @paulsc96 @thommythomaso

.github/workflows/ci.yml

@@ -36,19 +36,19 @@ jobs:
           submodules: 'recursive'
       - name: Build Software
         run: |
+          bender vendor init
           make -C target/snitch_cluster sw
       - name: Build Hardware
         run: |
           make -C target/snitch_cluster bin/snitch_cluster.vlt
       - name: Run Tests
         working-directory: target/snitch_cluster
-        run: |-
-          ../../util/sim/simulate.py sw/run.yaml --simulator verilator -j \
-          --verbose
+        run: |
+          ./run.py sw/run.yaml --simulator verilator -j
 
-  ############################################
+  #########################################
   # Build SW on Snitch Cluster w/ Banshee #
-  ############################################
+  #########################################
 
   sw-snitch-cluster-banshee:
     name: Simulate SW on Snitch Cluster w/ Banshee
@@ -61,11 +61,11 @@ jobs:
           submodules: 'recursive'
       - name: Build Software
         run: |
+          bender vendor init
           make -C target/snitch_cluster SELECT_RUNTIME=banshee sw
       - name: Run Tests
         env:
           SNITCH_LOG: info
         working-directory: target/snitch_cluster
-        run: |-
-          ../../util/sim/simulate.py sw/run.yaml --simulator banshee -j \
-          --verbose
+        run: |
+          ./run.py sw/run.yaml --simulator banshee -j

.gitlab-ci.yml

@@ -5,23 +5,32 @@
 variables:
   GIT_STRATEGY: clone
   GIT_SUBMODULE_STRATEGY: recursive
+  # Enable colors in CI terminal
+  TERM: ansi
+  FORCE_COLOR: 1
+  # Configure environment
   PYTHON: /usr/local/anaconda3-2022.05/bin/python3
   BENDER: bender-0.27.1
   CC: gcc-9.2.0
   CXX: g++-9.2.0
-  VCS: vcs-2020.12
-  VERILATOR: verilator-4.110
-  QUESTA: questa-2022.3
+  VCS_SEPP: vcs-2020.12
+  VERILATOR_SEPP: verilator-4.110
+  QUESTA_SEPP: questa-2022.3
   LLVM_BINROOT: /usr/pack/riscv-1.0-kgf/pulp-llvm-0.12.0/bin
-  CLANG: /usr/pack/riscv-1.0-kgf/pulp-llvm-0.12.0/bin/clang
   CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_LINKER: /usr/pack/gcc-9.2.0-af/linux-x64/bin/gcc
   LLVM_SYS_120_PREFIX: /usr/pack/llvm-12.0.1-af
   CMAKE: cmake-3.18.1
 
 before_script:
   - $PYTHON -m venv .venv
   - source .venv/bin/activate
-  - pip install -r python-requirements.txt
+  # Unpack packages in a local temporary directory which can be safely cleaned
+  # after installation. Also protects against "No space left on device" errors
+  # occurring when the /tmp folder is filled by other processes.
+  - mkdir tmp
+  - TMPDIR=tmp pip install -r python-requirements.txt
+  - rm -rf tmp
+  - $BENDER vendor init
 
 ##############
 # Build docs #
@@ -79,8 +88,8 @@ snitch-ip-tests:
           - tcdm_interface
   script:
     - cd hw/$IP
-    - $QUESTA ./util/compile.sh
-    - $QUESTA ./util/run_vsim.sh
+    - ./util/compile.sh
+    - ./util/run_vsim.sh
 
 ########################
 # Snitch cluster tests #
@@ -89,29 +98,26 @@ snitch-ip-tests:
 # Verilator
 snitch-cluster-vlt:
   needs: [snitch-cluster-sw]
-  # yamllint disable rule:line-length
   script:
     - cd target/snitch_cluster
-    - $VERILATOR make bin/snitch_cluster.vlt
-    - $VERILATOR ../../util/sim/simulate.py sw/run.yaml --simulator verilator -j --verbose
-  # yamllint enable rule:line-length
+    - make bin/snitch_cluster.vlt
+    - ./run.py sw/run.yaml --simulator verilator -j --run-dir runs/vlt
 
 # VCS
 snitch-cluster-vcs:
   needs: [snitch-cluster-sw]
   script:
     - cd target/snitch_cluster
-    - $VCS make bin/snitch_cluster.vcs
-    - $VCS ../../util/sim/simulate.py sw/run.yaml --simulator vcs -j --verbose
+    - make bin/snitch_cluster.vcs
+    - ./run.py sw/run.yaml --simulator vcs -j --run-dir runs/vcs
 
 # Questa
 snitch-cluster-vsim:
   needs: [snitch-cluster-sw]
   script:
     - cd target/snitch_cluster
-    - $QUESTA make bin/snitch_cluster.vsim
-    - $QUESTA ../../util/sim/simulate.py sw/run.yaml --simulator vsim -j
-      --verbose
+    - make bin/snitch_cluster.vsim
+    - ./run.py sw/run.yaml --simulator vsim -j --run-dir runs/vsim
 
 # Banshee
 snitch-cluster-banshee:
@@ -127,4 +133,4 @@ snitch-cluster-banshee:
     - cd banshee
     - cargo install --debug --path .
     - cd ../target/snitch_cluster
-    - ../../util/sim/simulate.py sw/run.yaml --simulator banshee -j --verbose
+    - ./run.py sw/run.yaml --simulator banshee -j --run-dir runs/banshee

Bender.yml

@@ -22,7 +22,7 @@ dependencies:
   axi:                { git: https://github.com/pulp-platform/axi,                version:  0.39.0  }
   axi_riscv_atomics:  { git: https://github.com/pulp-platform/axi_riscv_atomics,  version:  0.6.0   }
   common_cells:       { git: https://github.com/pulp-platform/common_cells,       version:  1.28.0  }
-  FPnew:              { git: https://github.com/openhwgroup/cvfpu,                rev:      1202ca3 }  # TODO: feature branch `feature/expanding_sdotp`; get merged!
+  FPnew:              { git: "https://github.com/pulp-platform/cvfpu.git",        rev:      pulp-v0.1.3 }
   register_interface: { git: https://github.com/pulp-platform/register_interface, version:  0.4.2   }
   tech_cells_generic: { git: https://github.com/pulp-platform/tech_cells_generic, version:  0.2.11  }
   riscv-dbg:          { git: https://github.com/pulp-platform/riscv-dbg,          version:  0.8.0   }
@@ -37,13 +37,40 @@ vendor_package:
       - "Makefile"
       - ".gitignore"
       - "README"
-      - "src/math/tanh.c"
+      - "src/math/ceil.c"
+      - "src/math/ceilf.c"
+      - "src/math/ceill.c"
       - "src/math/expm1.c"
+      - "src/math/expf.c"
+      - "src/math/exp2f_data.c"
+      - "src/math/exp2f_data.h"
+      - "src/math/log2.c"
+      - "src/math/log2_data.c"
+      - "src/math/log2_data.h"
+      - "src/math/log2f.c"
+      - "src/math/log2f_data.c"
+      - "src/math/log2f_data.h"
+      - "src/math/__math_divzero.c"
+      - "src/math/__math_invalid.c"
+      - "src/math/__math_invalidf.c"
+      - "src/math/__math_invalidl.c"
+      - "src/math/__math_oflow.c"
+      - "src/math/__math_oflowf.c"
+      - "src/math/__math_uflow.c"
+      - "src/math/__math_uflowf.c"
+      - "src/math/__math_xflow.c"
+      - "src/math/__math_xflowf.c"
+      - "src/math/sqrt.c"
+      - "src/math/sqrtf.c"
+      - "src/math/sqrt_data.c"
+      - "src/math/sqrt_data.h"
+      - "src/math/tanh.c"
       - "src/internal/libm.h"
       - "src/include/features.h"
       - "include/endian.h"
       - "include/math.h"
       - "include/features.h"
+      - "include/float.h"
       - "include/alltypes.h.in"
       - "arch/riscv64/bits/alltypes.h.in"
       - "arch/riscv64/bits/float.h"

Makefile

@@ -2,7 +2,8 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
-REGGEN = $(shell bender path register_interface)/vendor/lowrisc_opentitan/util/regtool.py
+BENDER ?= bender
+REGGEN  = $(shell $(BENDER) path register_interface)/vendor/lowrisc_opentitan/util/regtool.py
 
 GENERATED_DOCS_DIR = docs/generated
 GENERATED_DOC_SRCS = $(GENERATED_DOCS_DIR)/peripherals.md
@@ -16,9 +17,7 @@ clean: clean-docs
 doc-srcs: $(GENERATED_DOC_SRCS)
 
 docs: doc-srcs
-	@if mkdocs build | grep -q "ERROR"; then \
-		exit 1; \
-	fi
+	mkdocs build
 
 clean-docs:
 	rm -rf $(GENERATED_DOCS_DIR)

README.md

@@ -86,19 +86,39 @@ If you use the Snitch cluster or its extensions in your work, you can cite us:
 </details>
 
 <details>
-<summary><b>Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra</b></summary>
+<summary><b>Sparse Stream Semantic Registers: A Lightweight ISA Extension Accelerating General Sparse Linear Algebra</b></summary>
 <p>
 
 ```
-@inproceedings{scheffler2021indirect,
+@article{scheffler2023sparsessr,
   author={Scheffler, Paul and Zaruba, Florian and Schuiki, Fabian and Hoefler, Torsten and Benini, Luca},
-  booktitle={2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)},
-  title={Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra},
-  year={2021},
+  journal={IEEE Transactions on Parallel and Distributed Systems},
+  title={Sparse Stream Semantic Registers: A Lightweight ISA Extension Accelerating General Sparse Linear Algebra},
+  year={2023},
+  volume={34},
+  number={12},
+  pages={3147-3161},
+  doi={10.1109/TPDS.2023.3322029}
+}
+```
+
+</p>
+</details>
+
+<details>
+<summary><b>A High-performance, Energy-efficient Modular DMA Engine Architecture</b></summary>
+<p>
+
+```
+@ARTICLE{benz2023idma,
+  author={Benz, Thomas and Rogenmoser, Michael and Scheffler, Paul and Riedel, Samuel and Ottaviano, Alessandro and Kurth, Andreas and Hoefler, Torsten and Benini, Luca},
+  journal={IEEE Transactions on Computers},
+  title={A High-performance, Energy-efficient Modular DMA Engine Architecture},
+  year={2023},
   volume={},
   number={},
-  pages={1787-1792}
-}
+  pages={1-14},
+  doi={10.1109/TC.2023.3329930}}
 ```
 
 </p>

apt-requirements.txt

@@ -6,8 +6,4 @@
 clang-format
 device-tree-compiler
 graphviz
-python3
-python3-pip
-python3-setuptools
-python3-wheel
 tar

docs/publications.md

@@ -42,19 +42,39 @@ If you use the Snitch cluster or its extensions in your work, you can cite us:
 </details>
 
 <details>
-<summary><b>Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra</b></summary>
+<summary><b>Sparse Stream Semantic Registers: A Lightweight ISA Extension Accelerating General Sparse Linear Algebra</b></summary>
 <p>
 
 ```
-@inproceedings{scheffler2021indirect,
+@article{scheffler2023sparsessr,
   author={Scheffler, Paul and Zaruba, Florian and Schuiki, Fabian and Hoefler, Torsten and Benini, Luca},
-  booktitle={2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)},
-  title={Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra},
-  year={2021},
+  journal={IEEE Transactions on Parallel and Distributed Systems},
+  title={Sparse Stream Semantic Registers: A Lightweight ISA Extension Accelerating General Sparse Linear Algebra},
+  year={2023},
+  volume={34},
+  number={12},
+  pages={3147-3161},
+  doi={10.1109/TPDS.2023.3322029}
+}
+```
+
+</p>
+</details>
+
+<details>
+<summary><b>A High-performance, Energy-efficient Modular DMA Engine Architecture</b></summary>
+<p>
+
+```
+@ARTICLE{benz2023idma,
+  author={Benz, Thomas and Rogenmoser, Michael and Scheffler, Paul and Riedel, Samuel and Ottaviano, Alessandro and Kurth, Andreas and Hoefler, Torsten and Benini, Luca},
+  journal={IEEE Transactions on Computers},
+  title={A High-performance, Energy-efficient Modular DMA Engine Architecture},
+  year={2023},
   volume={},
   number={},
-  pages={1787-1792}
-}
+  pages={1-14},
+  doi={10.1109/TC.2023.3329930}}
 ```
 
 </p>

docs/requirements.txt

@@ -4,7 +4,8 @@
 
 # Keep sorted.
 mkdocs
-# Last version compatible with python-3.6 (default on Ubuntu 18.04)
-mkdocs-material <= 8.2.11
+mkdocs-material
 mkdocs-include-markdown-plugin
-mkdocs-macros-plugin
+mkdocs-macros-plugin
+mkdocstrings
+mkdocstrings-python

docs/rm/custom_instructions.md

@@ -37,7 +37,7 @@ The FREP instruction has the following signature:
 | max_inst | max_rpt | stagger_max | stagger_mask | 0        | OP-CUSTOM1 | FREP.I    |
 | max_inst | max_rpt | stagger_max | stagger_mask | 1        | OP-CUSTOM1 | FREP.O    |
 
-FREP.I and FREP.O repeat the *max_inst* instructions following the FREP instruction for *max_rpt + 1* times. The FREP.I instruction (*I* stands for inner) repeats every instruction the specified number of times and moves on to executing and repeating the next. The FREP.O instruction (*O* stands for outer) repeats the whole sequence of instructions *max_rpt + 1* times. Register staggering can be enabled and configured via the *stagger_mask* and *stagger_max* immediates. A detailed explanation of their use can be found in the Snitch [paper](/publications).
+FREP.I and FREP.O repeat the *max_inst + 1* instructions following the FREP instruction for *max_rpt + 1* times. The FREP.I instruction (*I* stands for inner) repeats every instruction the specified number of times and moves on to executing and repeating the next. The FREP.O instruction (*O* stands for outer) repeats the whole sequence of instructions *max_rpt + 1* times. Register staggering can be enabled and configured via the *stagger_mask* and *stagger_max* immediates. A detailed explanation of their use can be found in the Snitch [paper](/publications).
 
 The assembly instruction signature follows:
 

docs/rm/sim/Simulation.md

@@ -0,0 +1 @@
+::: Simulation

docs/rm/sim/Simulator.md

@@ -0,0 +1 @@
+::: Simulator

docs/rm/sim/sim_utils.md

@@ -0,0 +1 @@
+::: sim_utils

hw/mem_interface/util/compile.sh

@@ -10,11 +10,11 @@ set -e
 
 [ ! -z "$VSIM" ] || VSIM=vsim
 
-bender script vsim -t test \
+$BENDER script vsim -t test \
     --vlog-arg="-svinputport=compat" \
     --vlog-arg="-override_timescale 1ns/1ps" \
     --vlog-arg="-suppress 2583" \
     --vlog-arg="+cover=sbecft" \
     > compile.tcl
 echo 'return 0' >> compile.tcl
-$VSIM -c -do 'exit -code [source compile.tcl]'
+$QUESTA_SEPP $VSIM -c -do 'exit -code [source compile.tcl]'

hw/mem_interface/util/run_vsim.sh

@@ -12,7 +12,7 @@ ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)
 [ ! -z "$VSIM" ] || VSIM=vsim
 
 call_vsim() {
-    echo "log -r /*; run -all" | $VSIM -c -coverage -voptargs='+acc +cover=sbecft' "$@" | tee vsim.log 2>&1
+    echo "log -r /*; run -all" | $QUESTA_SEPP $VSIM -c -coverage -voptargs='+acc +cover=sbecft' "$@" | tee vsim.log 2>&1
     grep "Errors: 0," vsim.log
 }
 

hw/reqrsp_interface/util/compile.sh

@@ -10,11 +10,11 @@ set -e
 
 [ ! -z "$VSIM" ] || VSIM=vsim
 
-bender script vsim -t test \
+$(BENDER) script vsim -t test \
     --vlog-arg="-svinputport=compat" \
     --vlog-arg="-override_timescale 1ns/1ps" \
     --vlog-arg="-suppress 2583" \
     --vlog-arg="+cover=sbecft" \
     > compile.tcl
 echo 'return 0' >> compile.tcl
-$VSIM -c -do 'exit -code [source compile.tcl]'
+$QUESTA_SEPP $VSIM -c -do 'exit -code [source compile.tcl]'

hw/reqrsp_interface/util/run_vsim.sh

@@ -12,7 +12,7 @@ ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)
 [ ! -z "$VSIM" ] || VSIM=vsim
 
 call_vsim() {
-    echo "log -r /*; run -all" | $VSIM -c -coverage -voptargs='+acc +cover=sbecft' "$@" | tee vsim.log 2>&1
+    echo "log -r /*; run -all" | $QUESTA_SEPP $VSIM -c -coverage -voptargs='+acc +cover=sbecft' "$@" | tee vsim.log 2>&1
     grep "Errors: 0," vsim.log
 }
 

hw/snitch_cluster/src/snitch_cc.sv

@@ -487,6 +487,7 @@ module snitch_cc #(
       .trace_port_o            ( fpu_trace           ),
       .sequencer_tracer_port_o ( fpu_sequencer_trace ),
       // pragma translate_on
+      .hart_id_i        ( hart_id_i      ),
       .acc_req_i        ( acc_snitch_req ),
       .acc_req_valid_i  ( acc_qvalid     ),
       .acc_req_ready_o  ( acc_qready     ),