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hw: Replace $display with $info
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colluca committed Sep 28, 2024
1 parent 025e76d commit 5666230
Showing 1 changed file with 6 additions and 6 deletions.
12 changes: 6 additions & 6 deletions hw/snitch/src/snitch.sv
Original file line number Diff line number Diff line change
Expand Up @@ -2241,8 +2241,8 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
// pragma translate_off
always_ff @(posedge clk_i) begin
if (!rst_i && illegal_inst && valid_instr) begin
$display("%t [Illegal Instruction Core %0d] PC: %h Data: %h",
$time, hart_id_i, inst_addr_o, inst_data_i);
$info("[Illegal Instruction Core %0d] PC: %h Data: %h",
hart_id_i, inst_addr_o, inst_data_i);
end
end
// pragma translate_on
Expand Down Expand Up @@ -2616,8 +2616,8 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
// Display CSR write if the CSR does not exist
if (!rst_i && csr_dump && inst_valid_o && inst_ready_i && !stall) begin
// $timeformat(-9, 0, " ns", 0);
$display("[DUMP] %t Core %3d: 0x%3h = 0x%08h, %d, %f",
$time, hart_id_i, inst_data_i[31:20], alu_result, alu_result, $bitstoshortreal(alu_result));
$display("[Dump Core %0d] %t 0x%3h = 0x%08h, %d, %f", hart_id_i,
$time, inst_data_i[31:20], alu_result, alu_result, $bitstoshortreal(alu_result));
end
end
// pragma translate_on
Expand Down Expand Up @@ -2887,8 +2887,8 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
// pragma translate_off
always_ff @(posedge clk_i) begin
if (!rst_i && (ld_addr_misaligned || st_addr_misaligned) && valid_instr) begin
$display("%t [Misaligned Load/Store Core %0d] PC: %h Data: %h Addr: %h",
$time, hart_id_i, inst_addr_o, inst_data_i, alu_result);
$info("[Misaligned Load/Store Core %0d] PC: %h Data: %h Addr: %h",
hart_id_i, inst_addr_o, inst_data_i, alu_result);
end
end
// pragma translate_on
Expand Down

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