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docs: Adapt documentation and schemas for new repository
* clustergen: Require absolute paths to schemas * ci: Freeze verible_version for CI checks * doc: Update directory structure documenation to include README's of the main directories and add mkdocs-include-markdown-plugin as requirement * doc: Update overall documentation * docs: Reduce redundancy and organize user guide in a linear way * ci: Update to new version of `pulp-actions` *.github: Add CODEOWNERS file * doc: Add README.md * doc: Clean up publications, keep only cluster-related works * doc: Address review feedback * doc: Build on `main` branch * doc: Some fixes --------- Co-authored-by: Luca Colagrande <[email protected]> Co-authored-by: Paul Scheffler <[email protected]>
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| # These owners will be the default owners for everything in the repo. | ||
| # Unless a later match takes precedence, global owners below will be | ||
| # requested for review when someone opens a pull request. | ||
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| * @paulsc96 @colluca | ||
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| hw/snitch_cluster @paulsc96 @lucabertaccini | ||
| hw/snitch_dma @paulsc96 @thommythomaso | ||
| hw/snitch_icache @paulsc96 @SamuelRiedel | ||
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| sw @colluca @fischeti @viv-eth |
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|  | ||
| [](https://opensource.org/licenses/Apache-2.0) | ||
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| # Snitch Cluster | ||
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| This repository hosts the hardware and software for the Snitch cluster and its generator. Snitch is a high-efficiency compute cluster platform focused on floating-point workloads. It is developed as part of the PULP project, a joint effort between ETH Zurich and the University of Bologna. | ||
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| ## Getting Started | ||
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| To get started, check out the [getting started guide](https://pulp-platform.github.io/snitch_cluster/ug/getting_started.html). | ||
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| ## Content | ||
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| What can you expect to find in this repository? | ||
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| - The RISC-V [Snitch integer core](https://pulp-platform.github.io/snitch_cluster/rm/snitch/). This can be useful stand-alone if you are just interested in re-using the core for your project, e.g., as a tiny control core or you want to make a peripheral smart. The sky is the limit. | ||
| - The [Snitch cluster](https://pulp-platform.github.io/snitch_cluster/ug/snitch_cluster/). A highly configurable cluster containing one to many integer cores with optional floating-point capabilities as well as our custom ISA extensions `Xssr`, `Xfrep`, and `Xdma`. | ||
| - A runtime and example applications for the Snitch cluster. | ||
| - RTL simulation environments for Verilator, Questa Advanced Simulator, and VCS, as well as configurations for our [Banshee system simulator](https://github.com/pulp-platform/banshee) | ||
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| This code was previously hosted in the [Snitch monorepo](https://github.com/pulp-platform/snitch) and was spun off into its own repository to simplify maintenance and dependency handling. Note that our Snitch-based manycore system [Occamy](https://github.com/pulp-platform/occamy) has also moved. | ||
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| ## Tool Requirements | ||
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| * `verilator >= v4.1` | ||
| * `bender >= v0.27.0` | ||
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| ## License | ||
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| Snitch is being made available under permissive open source licenses. | ||
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| The following files are released under Apache License 2.0 (`Apache-2.0`) see `LICENSE`: | ||
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| - `sw/` | ||
| - `util/` | ||
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| The following files are released under Solderpad v0.51 (`SHL-0.51`) see `hw/LICENSE`: | ||
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| - `hw/` | ||
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| The `sw/deps` directory references submodules that come with their own | ||
| licenses. See the respective folder for the licenses used. | ||
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| - `sw/deps/` | ||
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| ## Publications | ||
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| If you use the Snitch cluster or its extensions in your work, you can cite us: | ||
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| <details> | ||
| <summary><b>Snitch: A tiny Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads</b></summary> | ||
| <p> | ||
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| ``` | ||
| @article{zaruba2020snitch, | ||
| title={Snitch: A tiny Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads}, | ||
| author={Zaruba, Florian and Schuiki, Fabian and Hoefler, Torsten and Benini, Luca}, | ||
| journal={IEEE Transactions on Computers}, | ||
| year={2020}, | ||
| publisher={IEEE} | ||
| } | ||
| ``` | ||
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| </p> | ||
| </details> | ||
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| <details> | ||
| <summary><b>Stream semantic registers: A lightweight risc-v isa extension achieving full compute utilization in single-issue cores</b></summary> | ||
| <p> | ||
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| ``` | ||
| @article{schuiki2020stream, | ||
| title={Stream semantic registers: A lightweight risc-v isa extension achieving full compute utilization in single-issue cores}, | ||
| author={Schuiki, Fabian and Zaruba, Florian and Hoefler, Torsten and Benini, Luca}, | ||
| journal={IEEE Transactions on Computers}, | ||
| volume={70}, | ||
| number={2}, | ||
| pages={212--227}, | ||
| year={2020}, | ||
| publisher={IEEE} | ||
| } | ||
| ``` | ||
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| </p> | ||
| </details> | ||
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| <details> | ||
| <summary><b>Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra</b></summary> | ||
| <p> | ||
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| ``` | ||
| @inproceedings{scheffler2021indirect, | ||
| author={Scheffler, Paul and Zaruba, Florian and Schuiki, Fabian and Hoefler, Torsten and Benini, Luca}, | ||
| booktitle={2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)}, | ||
| title={Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra}, | ||
| year={2021}, | ||
| volume={}, | ||
| number={}, | ||
| pages={1787-1792} | ||
| } | ||
| ``` | ||
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| </p> | ||
| </details> | ||
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| <details> | ||
| <summary><b>MiniFloat-NN and ExSdotp: An ISA Extension and a Modular Open Hardware Unit for Low-Precision Training on RISC-V Cores</b></summary> | ||
| <p> | ||
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| ``` | ||
| @inproceedings{bertaccini2022minifloat, | ||
| author={Bertaccini, Luca and Paulin, Gianna and Fischer, Tim and Mach, Stefan and Benini, Luca}, | ||
| booktitle={2022 IEEE 29th Symposium on Computer Arithmetic (ARITH)}, | ||
| title={MiniFloat-NN and ExSdotp: An ISA Extension and a Modular Open Hardware Unit for Low-Precision Training on RISC-V Cores}, | ||
| year={2022}, | ||
| volume={}, | ||
| number={}, | ||
| pages={1-8} | ||
| } | ||
| ``` | ||
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| </p> | ||
| </details> | ||
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| <details> | ||
| <summary><b>Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters</b></summary> | ||
| <p> | ||
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| ``` | ||
| @inproceedings{paulin2022softtiles, | ||
| author={Paulin, Gianna and Cavalcante, Matheus and Scheffler, Paul and Bertaccini, Luca and Zhang, Yichao and Gürkaynak, Frank and Benini, Luca}, | ||
| booktitle={2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)}, | ||
| title={Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters}, | ||
| year={2022}, | ||
| volume={}, | ||
| number={}, | ||
| pages={44-49}, | ||
| doi={10.1109/ISVLSI54635.2022.00021} | ||
| } | ||
| ``` | ||
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| </p> |
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| # Publications | ||
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| The Snitch architecture is built on research that is described in the following publications. | ||
| If you use the Snitch cluster or its extensions in your work, you can cite us: | ||
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| ## 2021 | ||
| <details> | ||
| <summary><b>Snitch: A tiny Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads</b></summary> | ||
| <p> | ||
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| F. Zaruba, F. Schuiki, T. Hoefler and L. Benini, "Snitch: A Tiny Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads," in IEEE Transactions on Computers, vol. 70, no. 11, pp. 1845-1860, 1 Nov. 2021, [doi: 10.1109/TC.2020.3027900](http://www.doi.org/10.1109/TC.2020.3027900). | ||
| ``` | ||
| @article{zaruba2020snitch, | ||
| title={Snitch: A tiny Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads}, | ||
| author={Zaruba, Florian and Schuiki, Fabian and Hoefler, Torsten and Benini, Luca}, | ||
| journal={IEEE Transactions on Computers}, | ||
| year={2020}, | ||
| publisher={IEEE} | ||
| } | ||
| ``` | ||
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| F. Schuiki, F. Zaruba, T. Hoefler and L. Benini, "Stream Semantic Registers: A Lightweight RISC-V ISA Extension Achieving Full Compute Utilization in Single-Issue Cores," in IEEE Transactions on Computers, vol. 70, no. 2, pp. 212-227, 1 Feb. 2021, [doi: 10.1109/TC.2020.2987314](http://www.doi.org/10.1109/TC.2020.2987314). | ||
| </p> | ||
| </details> | ||
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| S. Riedel, F. Schuiki, P. Scheffler, F. Zaruba and L. Benini, "Banshee: A Fast LLVM-Based RISC-V Binary Translator," 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2021, pp. 1-9, [doi: 10.1109/ICCAD51958.2021.9643546](http://www.doi.org/10.1109/ICCAD51958.2021.9643546). | ||
| <details> | ||
| <summary><b>Stream semantic registers: A lightweight risc-v isa extension achieving full compute utilization in single-issue cores</b></summary> | ||
| <p> | ||
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| F. Zaruba, F. Schuiki and L. Benini, "Manticore: A 4096-Core RISC-V Chiplet Architecture for Ultraefficient Floating-Point Computing," in IEEE Micro, vol. 41, no. 2, pp. 36-42, 1 March-April 2021, [doi: 10.1109/MM.2020.3045564](http://www.doi.org/10.1109/MM.2020.3045564). | ||
| ``` | ||
| @article{schuiki2020stream, | ||
| title={Stream semantic registers: A lightweight risc-v isa extension achieving full compute utilization in single-issue cores}, | ||
| author={Schuiki, Fabian and Zaruba, Florian and Hoefler, Torsten and Benini, Luca}, | ||
| journal={IEEE Transactions on Computers}, | ||
| volume={70}, | ||
| number={2}, | ||
| pages={212--227}, | ||
| year={2020}, | ||
| publisher={IEEE} | ||
| } | ||
| ``` | ||
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| P. Scheffler, F. Zaruba, F. Schuiki, T. Hoefler and L. Benini, "Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra," 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021, pp. 1787-1792, [doi: 10.23919/DATE51398.2021.9474230](http://www.doi.org/10.23919/DATE51398.2021.9474230). | ||
| </p> | ||
| </details> | ||
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| <details> | ||
| <summary><b>Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra</b></summary> | ||
| <p> | ||
|
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| ``` | ||
| @inproceedings{scheffler2021indirect, | ||
| author={Scheffler, Paul and Zaruba, Florian and Schuiki, Fabian and Hoefler, Torsten and Benini, Luca}, | ||
| booktitle={2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)}, | ||
| title={Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra}, | ||
| year={2021}, | ||
| volume={}, | ||
| number={}, | ||
| pages={1787-1792} | ||
| } | ||
| ``` | ||
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| </p> | ||
| </details> | ||
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| <details> | ||
| <summary><b>MiniFloat-NN and ExSdotp: An ISA Extension and a Modular Open Hardware Unit for Low-Precision Training on RISC-V Cores</b></summary> | ||
| <p> | ||
|
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| ``` | ||
| @inproceedings{bertaccini2022minifloat, | ||
| author={Bertaccini, Luca and Paulin, Gianna and Fischer, Tim and Mach, Stefan and Benini, Luca}, | ||
| booktitle={2022 IEEE 29th Symposium on Computer Arithmetic (ARITH)}, | ||
| title={MiniFloat-NN and ExSdotp: An ISA Extension and a Modular Open Hardware Unit for Low-Precision Training on RISC-V Cores}, | ||
| year={2022}, | ||
| volume={}, | ||
| number={}, | ||
| pages={1-8} | ||
| } | ||
| ``` | ||
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| </p> | ||
| </details> | ||
|
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| <details> | ||
| <summary><b>Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters</b></summary> | ||
| <p> | ||
|
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| ``` | ||
| @inproceedings{paulin2022softtiles, | ||
| author={Paulin, Gianna and Cavalcante, Matheus and Scheffler, Paul and Bertaccini, Luca and Zhang, Yichao and Gürkaynak, Frank and Benini, Luca}, | ||
| booktitle={2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)}, | ||
| title={Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters}, | ||
| year={2022}, | ||
| volume={}, | ||
| number={}, | ||
| pages={44-49}, | ||
| doi={10.1109/ISVLSI54635.2022.00021} | ||
| } | ||
| ``` | ||
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| </p> |
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| ../../hw/reqrsp_interface/doc/index.md |
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