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periph: Update regfile sources
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@fischeti
fischeti committed Aug 5, 2024
1 parent 66adb56 commit 37e8435
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Showing 2 changed files with 14 additions and 54 deletions.
34 changes: 10 additions & 24 deletions hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -46,10 +46,6 @@ package snitch_cluster_peripheral_reg_pkg;
logic qe;
} snitch_cluster_peripheral_reg2hw_cl_clint_clear_reg_t;

typedef struct packed {
logic [31:0] q;
} snitch_cluster_peripheral_reg2hw_hw_barrier_reg_t;

typedef struct packed {
logic q;
} snitch_cluster_peripheral_reg2hw_icache_prefetch_enable_reg_t;
Expand All @@ -67,26 +63,20 @@ package snitch_cluster_peripheral_reg_pkg;
logic [47:0] d;
} snitch_cluster_peripheral_hw2reg_perf_cnt_mreg_t;

typedef struct packed {
logic [31:0] d;
} snitch_cluster_peripheral_hw2reg_hw_barrier_reg_t;

// Register -> HW type
typedef struct packed {
snitch_cluster_peripheral_reg2hw_perf_cnt_en_mreg_t [15:0] perf_cnt_en; // [1442:1427]
snitch_cluster_peripheral_reg2hw_perf_cnt_sel_mreg_t [15:0] perf_cnt_sel; // [1426:883]
snitch_cluster_peripheral_reg2hw_perf_cnt_mreg_t [15:0] perf_cnt; // [882:99]
snitch_cluster_peripheral_reg2hw_cl_clint_set_reg_t cl_clint_set; // [98:66]
snitch_cluster_peripheral_reg2hw_cl_clint_clear_reg_t cl_clint_clear; // [65:33]
snitch_cluster_peripheral_reg2hw_hw_barrier_reg_t hw_barrier; // [32:1]
snitch_cluster_peripheral_reg2hw_perf_cnt_en_mreg_t [15:0] perf_cnt_en; // [1410:1395]
snitch_cluster_peripheral_reg2hw_perf_cnt_sel_mreg_t [15:0] perf_cnt_sel; // [1394:851]
snitch_cluster_peripheral_reg2hw_perf_cnt_mreg_t [15:0] perf_cnt; // [850:67]
snitch_cluster_peripheral_reg2hw_cl_clint_set_reg_t cl_clint_set; // [66:34]
snitch_cluster_peripheral_reg2hw_cl_clint_clear_reg_t cl_clint_clear; // [33:1]
snitch_cluster_peripheral_reg2hw_icache_prefetch_enable_reg_t icache_prefetch_enable; // [0:0]
} snitch_cluster_peripheral_reg2hw_t;

// HW -> register type
typedef struct packed {
snitch_cluster_peripheral_hw2reg_perf_cnt_sel_mreg_t [15:0] perf_cnt_sel; // [1311:800]
snitch_cluster_peripheral_hw2reg_perf_cnt_mreg_t [15:0] perf_cnt; // [799:32]
snitch_cluster_peripheral_hw2reg_hw_barrier_reg_t hw_barrier; // [31:0]
snitch_cluster_peripheral_hw2reg_perf_cnt_sel_mreg_t [15:0] perf_cnt_sel; // [1279:768]
snitch_cluster_peripheral_hw2reg_perf_cnt_mreg_t [15:0] perf_cnt; // [767:0]
} snitch_cluster_peripheral_hw2reg_t;

// Register offsets
Expand Down Expand Up @@ -140,8 +130,7 @@ package snitch_cluster_peripheral_reg_pkg;
parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_15_OFFSET = 9'h 178;
parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET_OFFSET = 9'h 180;
parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR_OFFSET = 9'h 188;
parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_HW_BARRIER_OFFSET = 9'h 190;
parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE_OFFSET = 9'h 198;
parameter logic [BlockAw-1:0] SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE_OFFSET = 9'h 190;

// Reset values for hwext registers and their fields
parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_SEL_0_RESVAL = 32'h 0;
Expand Down Expand Up @@ -178,7 +167,6 @@ package snitch_cluster_peripheral_reg_pkg;
parameter logic [47:0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_15_RESVAL = 48'h 0;
parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET_RESVAL = 32'h 0;
parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR_RESVAL = 32'h 0;
parameter logic [31:0] SNITCH_CLUSTER_PERIPHERAL_HW_BARRIER_RESVAL = 32'h 0;

// Register index
typedef enum int {
Expand Down Expand Up @@ -232,12 +220,11 @@ package snitch_cluster_peripheral_reg_pkg;
SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_15,
SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET,
SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR,
SNITCH_CLUSTER_PERIPHERAL_HW_BARRIER,
SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE
} snitch_cluster_peripheral_id_e;

// Register width information to check illegal writes
parameter logic [3:0] SNITCH_CLUSTER_PERIPHERAL_PERMIT [52] = '{
parameter logic [3:0] SNITCH_CLUSTER_PERIPHERAL_PERMIT [51] = '{
4'b 0001, // index[ 0] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_0
4'b 0001, // index[ 1] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_1
4'b 0001, // index[ 2] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_2
Expand Down Expand Up @@ -288,8 +275,7 @@ package snitch_cluster_peripheral_reg_pkg;
4'b 1111, // index[47] SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_15
4'b 1111, // index[48] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET
4'b 1111, // index[49] SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR
4'b 1111, // index[50] SNITCH_CLUSTER_PERIPHERAL_HW_BARRIER
4'b 0001 // index[51] SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE
4'b 0001 // index[50] SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE
};

endpackage
Expand Down
34 changes: 4 additions & 30 deletions hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_top.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -312,8 +312,6 @@ module snitch_cluster_peripheral_reg_top #(
logic cl_clint_set_we;
logic [31:0] cl_clint_clear_wd;
logic cl_clint_clear_we;
logic [31:0] hw_barrier_qs;
logic hw_barrier_re;
logic icache_prefetch_enable_wd;
logic icache_prefetch_enable_we;

Expand Down Expand Up @@ -1572,22 +1570,6 @@ module snitch_cluster_peripheral_reg_top #(
);


// R[hw_barrier]: V(True)

prim_subreg_ext #(
.DW (32)
) u_hw_barrier (
.re (hw_barrier_re),
.we (1'b0),
.wd ('0),
.d (hw2reg.hw_barrier.d),
.qre (),
.qe (),
.q (reg2hw.hw_barrier.q ),
.qs (hw_barrier_qs)
);


// R[icache_prefetch_enable]: V(False)

prim_subreg #(
Expand Down Expand Up @@ -1616,7 +1598,7 @@ module snitch_cluster_peripheral_reg_top #(



logic [51:0] addr_hit;
logic [50:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[ 0] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_EN_0_OFFSET);
Expand Down Expand Up @@ -1669,8 +1651,7 @@ module snitch_cluster_peripheral_reg_top #(
addr_hit[47] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_PERF_CNT_15_OFFSET);
addr_hit[48] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET_OFFSET);
addr_hit[49] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR_OFFSET);
addr_hit[50] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_HW_BARRIER_OFFSET);
addr_hit[51] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE_OFFSET);
addr_hit[50] = (reg_addr == SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE_OFFSET);
end

assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
Expand Down Expand Up @@ -1728,8 +1709,7 @@ module snitch_cluster_peripheral_reg_top #(
(addr_hit[47] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[47] & ~reg_be))) |
(addr_hit[48] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[48] & ~reg_be))) |
(addr_hit[49] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[49] & ~reg_be))) |
(addr_hit[50] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[50] & ~reg_be))) |
(addr_hit[51] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[51] & ~reg_be)))));
(addr_hit[50] & (|(SNITCH_CLUSTER_PERIPHERAL_PERMIT[50] & ~reg_be)))));
end

assign perf_cnt_en_0_we = addr_hit[0] & reg_we & !reg_error;
Expand Down Expand Up @@ -1978,9 +1958,7 @@ module snitch_cluster_peripheral_reg_top #(
assign cl_clint_clear_we = addr_hit[49] & reg_we & !reg_error;
assign cl_clint_clear_wd = reg_wdata[31:0];

assign hw_barrier_re = addr_hit[50] & reg_re & !reg_error;

assign icache_prefetch_enable_we = addr_hit[51] & reg_we & !reg_error;
assign icache_prefetch_enable_we = addr_hit[50] & reg_we & !reg_error;
assign icache_prefetch_enable_wd = reg_wdata[0];

// Read data return
Expand Down Expand Up @@ -2204,10 +2182,6 @@ module snitch_cluster_peripheral_reg_top #(
end

addr_hit[50]: begin
reg_rdata_next[31:0] = hw_barrier_qs;
end

addr_hit[51]: begin
reg_rdata_next[0] = '0;
end

Expand Down

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