hw: Fully gate debug support in Snitch core #576
paulsc96
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lint.yml
on: push
Lint Verilog sources
1m 1s
Check bender vendor up-to-date
21s
Check Opcodes Up-to-Date
6s
Check License headers
10s
Lint YAML Sources
3s
Lint Python Sources
10s
Lint C/C++ Sources
12s
Lint Editorconfig
8s
Annotations
1 error and 3 warnings
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Lint Verilog sources
Process completed with exit code 1.
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Check License headers
The following actions uses node12 which is deprecated and will be forced to run on node16: actions/setup-python@v2. For more info: https://github.blog/changelog/2023-06-13-github-actions-all-actions-will-run-on-node16-instead-of-node12-by-default/
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[verible-verilog-lint] hw/snitch/src/snitch.sv#L487:
hw/snitch/src/snitch.sv#L487
Line length exceeds max: 100; is: 109 [Style: line-length] [line-length]
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[verible-verilog-lint] hw/snitch/src/snitch.sv#L487:
hw/snitch/src/snitch.sv#L487
Line length exceeds max: 100; is: 109 [Style: line-length] [line-length]
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