v2.0.0: Major interconnect changes

Added

• Completely replaced soc_interconnect with a new parametric version
• Added AXI Crossbar to soc_interconnect to attach custom IPs
• Added new pulp_soc parameter to isolate the axi plug CDC fifo in case it is not needed
• Add register_interface as dependency to simplify integration of custom ip using reggen
• Properly assert r_opc signal in new interconnect to indicate bus errors
• Add error checking for illegal access on HWPE ports which only have access to L2 interleaved memory

Changed

• AXI ID width of cluster plugs are now set to actually required width instead of a hardcoded one
• TCDM protocol to SRAM specific protocol is moved from interconnect to memory bank module

Removed

• obsolete axi_node dependency
• obsolete header files