[RTL] 1.Add two flags in config.mk: spm_bank_id_remap and tile_id_rem…

…ap to control the spm bank id remapping inside of each tile, and tile id remapping inside of each group. Modulize related rtl code.

      2.Debug: move the core request tile id remapping from after soc/local/remote tile demux to address_scrambler. Before, the core can access wrong local/remote port.

Bender.yml

@@ -37,6 +37,8 @@ sources:
   - hardware/src/bootrom.sv
   - hardware/src/latch_scm.sv
   - hardware/src/selector.sv
+  - hardware/src/mempool_tile_id_remapper.sv
+  - hardware/src/mempool_group_tile_id_remapper.sv
   # Level 1
   - hardware/src/mempool_tile.sv
   # Level 3

config/config.mk

@@ -77,5 +77,11 @@ xDivSqrt ?= 0
 l2_sim_type ?= sram
 dram_axi_width_interleaved ?= 16
 
+# Enable SPM bank id remapping inside of each tile
+spm_bank_id_remap ?= 0
+
+# Enable tile id remapping inside of each group
+tile_id_remap ?= 1
+
 # Enable the spm access pattern profiling
 spm_profiling ?= 0

hardware/Makefile

@@ -146,6 +146,12 @@ vlog_defs += -DDRAM_AXI_WIDTH_INTERLEAVED=${dram_axi_width_interleaved}
 ifeq (1, $(spm_profiling))
 	vlog_defs += -DSPM_PROFILING=$(spm_profiling)
 endif
+ifeq (1, $(spm_bank_id_remap))
+	vlog_defs += -DSPM_BANK_ID_REMAP=$(spm_bank_id_remap)
+endif
+ifeq (1, $(tile_id_remap))
+	vlog_defs += -DTILE_ID_REMAP=$(tile_id_remap)
+endif
 
 # Traffic generation enabled
 ifdef tg

hardware/src/address_scrambler.sv

@@ -12,6 +12,7 @@ module address_scrambler #(
   parameter int unsigned AddrWidth         = 32,
   parameter int unsigned ByteOffset        = 2,
   parameter int unsigned NumTiles          = 2,
+  parameter int unsigned NumTilesPerDma    = 16,
   parameter int unsigned NumBanksPerTile   = 2,
   parameter bit          Bypass            = 0,
   parameter int unsigned SeqMemSizePerTile = 4*1024
@@ -21,11 +22,23 @@ module address_scrambler #(
 );
   localparam int unsigned BankOffsetBits    = $clog2(NumBanksPerTile);
   localparam int unsigned TileIdBits        = $clog2(NumTiles);
+  localparam int unsigned TileIdBitsPerDma  = $clog2(NumTilesPerDma);
   localparam int unsigned SeqPerTileBits    = $clog2(SeqMemSizePerTile);
   localparam int unsigned SeqTotalBits      = SeqPerTileBits+TileIdBits;
   localparam int unsigned ConstantBitsLSB   = ByteOffset + BankOffsetBits;
   localparam int unsigned ScrambleBits      = SeqPerTileBits-ConstantBitsLSB;
 
+  function automatic logic [TileIdBitsPerDma-1:0] spm_tile_id_remap (
+      logic [TileIdBitsPerDma-1:0] data_in,
+      logic [TileIdBitsPerDma-1:0] idx_i
+  );
+    `ifdef TILE_ID_REMAP
+      spm_tile_id_remap = data_in + idx_i;
+    `else
+      spm_tile_id_remap = data_in;
+    `endif
+  endfunction
+
   if (Bypass || NumTiles < 2) begin
     assign address_o = address_i;
   end else begin
@@ -52,6 +65,12 @@ module address_scrambler #(
       // If not in bypass mode and address is in sequential region and more than one tile
       if (address_i < (NumTiles * SeqMemSizePerTile)) begin
         address_o[SeqTotalBits-1:ConstantBitsLSB] = {scramble, tile_id};
+      end else begin
+        address_o[ConstantBitsLSB +: TileIdBitsPerDma] =
+          spm_tile_id_remap(
+            address_i[ConstantBitsLSB +: TileIdBitsPerDma],
+            address_i[(ConstantBitsLSB + TileIdBits) +: TileIdBitsPerDma]
+          );
       end
     end
   end

hardware/src/mempool_group.sv

@@ -418,8 +418,6 @@ module mempool_group
 
   `REQRSP_TYPEDEF_ALL(reqrsp, addr_t, axi_data_t, axi_strb_t)
 
-
-  logic        [NumDmasPerGroup-1:0][idx_width(NumTilesPerDma)-1:0] tile_id_remap_before;
   logic        [NumDmasPerGroup-1:0][idx_width(NumTilesPerDma)-1:0] tile_id_remap;
 
   for (genvar d = 0; unsigned'(d) < NumDmasPerGroup; d++) begin: gen_dmas
@@ -531,9 +529,12 @@ module mempool_group
       .reqrsp_rsp_i(dma_reqrsp_rsp)
     );
 
-    assign tile_id_remap_before[d] = dma_reqrsp_req.q.addr[(ByteOffset + idx_width(NumBanksPerTile)) +: idx_width(NumTilesPerDma)];
-    assign tile_id_remap[d] = dma_reqrsp_req.q.addr[(ByteOffset + idx_width(NumBanksPerTile)) +: idx_width(NumTilesPerDma)] + 
-                              dma_reqrsp_req.q.addr[(ByteOffset + idx_width(NumBanksPerTile) + idx_width(NumTilesPerGroup) + idx_width(NumGroups)) +: idx_width(NumTilesPerDma)];
+    mempool_group_tile_id_remapper #() 
+    i_mempool_group_tile_id_remapper (
+      .dma_reqrsp_req_i (dma_reqrsp_req),
+      .tile_id_remap_o  (tile_id_remap[d])
+    );
+
 
     if (NumTilesPerDma > 1) begin: gen_dma_reqrsp_demux
       reqrsp_demux #(

hardware/src/mempool_group_tile_id_remapper.sv

@@ -0,0 +1,22 @@
+module mempool_group_tile_id_remapper
+  import mempool_pkg::*;
+  import cf_math_pkg::idx_width;
+#(
+) (
+  input  reqrsp_req_t                                 dma_reqrsp_req_i,
+  output logic        [idx_width(NumTilesPerDma)-1:0] tile_id_remap_o
+);
+
+  logic        [idx_width(NumTilesPerDma)-1:0] tile_id_remap_before;
+  logic        [idx_width(NumTilesPerDma)-1:0] tile_id_remap;
+
+  assign tile_id_remap_before = dma_reqrsp_req_i.q.addr[(ByteOffset + idx_width(NumBanksPerTile)) +: idx_width(NumTilesPerDma)];
+  assign tile_id_remap        = tile_id_remap_before + 
+                                dma_reqrsp_req_i.q.addr[(ByteOffset + idx_width(NumBanksPerTile) + idx_width(NumTilesPerGroup) + idx_width(NumGroups)) +: idx_width(NumTilesPerDma)];
+
+  `ifdef TILE_ID_REMAP
+  assign tile_id_remap_o = tile_id_remap;
+  `else
+  assign tile_id_remap_o = tile_id_remap_before;
+  `endif
+endmodule

hardware/src/mempool_tile.sv

@@ -64,7 +64,6 @@ module mempool_tile
   /*****************
    *  Definitions  *
    *****************/
-  `define min(a,b) (((a) < (b))? (a) : (b))
 
   import snitch_pkg::dreq_t;
   import snitch_pkg::dresp_t;
@@ -74,17 +73,6 @@ module mempool_tile
   // Local interconnect address width
   typedef logic [idx_width(NumCoresPerTile + NumRemotePortsPerTile)-1:0] local_req_interco_addr_t;
 
-  localparam SHIFT_AMOUNT = `min(TCDMAddrMemWidth, idx_width(NumBanksPerTile)); // or 4
-
-  function automatic logic [idx_width(NumBanksPerTile)-1:0] spm_bank_id_remap (
-      logic [idx_width(NumBanksPerTile)-1:0] data_in,
-      logic [SHIFT_AMOUNT-1:0] idx_i
-  );
-      spm_bank_id_remap = data_in + idx_i;
-      // spm_bank_id_remap = data_in;
-  endfunction
-
-
   /*********************
    *  Control Signals  *
    *********************/
@@ -99,42 +87,13 @@ module mempool_tile
     assign group_id = '0;
   end: gen_group_id
 
-  /***********************
-   *  Bank Address Hash  *
-   ***********************/
+  /************************
+   *  Bank Address Remap  *
+   ************************/
   tcdm_dma_req_t                               tcdm_dma_req_remapped;
   tcdm_slave_req_t [NumRemotePortsPerTile-1:0] tcdm_slave_req_remapped;
-  tcdm_slave_req_t [NumCoresPerTile-1:0]       local_req_interco_payload;
   tcdm_slave_req_t [NumCoresPerTile-1:0]       local_req_interco_payload_remapped;
 
-
-  always_comb begin
-    tcdm_dma_req_remapped = tcdm_dma_req_i;
-    tcdm_dma_req_remapped.tgt_addr[idx_width(NumBanksPerTile)-1:0] = 
-        spm_bank_id_remap(
-          tcdm_dma_req_i.tgt_addr[idx_width(NumBanksPerTile)-1:0],
-          tcdm_dma_req_i.tgt_addr[idx_width(NumBanksPerTile) +: SHIFT_AMOUNT]
-        );
-
-    for(int rp = 0; rp < NumRemotePortsPerTile; rp++) begin
-      tcdm_slave_req_remapped[rp] = tcdm_slave_req_i[rp];
-      tcdm_slave_req_remapped[rp].tgt_addr[idx_width(NumBanksPerTile)-1:0] = 
-          spm_bank_id_remap(
-            tcdm_slave_req_i[rp].tgt_addr[idx_width(NumBanksPerTile)-1:0],
-            tcdm_slave_req_i[rp].tgt_addr[idx_width(NumBanksPerTile) +: SHIFT_AMOUNT]
-          );
-    end
-
-    for(int c = 0; c < NumCoresPerTile; c++) begin
-      local_req_interco_payload_remapped[c] = local_req_interco_payload[c];
-      local_req_interco_payload_remapped[c].tgt_addr[idx_width(NumBanksPerTile)-1:0] = 
-          spm_bank_id_remap(
-            local_req_interco_payload[c].tgt_addr[idx_width(NumBanksPerTile)-1:0],
-            local_req_interco_payload[c].tgt_addr[idx_width(NumBanksPerTile) +: SHIFT_AMOUNT]
-          );
-    end
-  end
-
   /***********
    *  Cores  *
    ***********/
@@ -749,67 +708,17 @@ module mempool_tile
   remote_ports_index_t [NumCoresPerTile-1:0] remote_req_interco_tgt_sel;
   remote_ports_index_t [NumCoresPerTile-1:0] remote_req_interco_tgt_sel_q;
   logic                [NumCoresPerTile-1:0] remote_req_interco_tgt_sel_q_update;
+  remote_ports_index_t [NumCoresPerTile-1:0] remote_req_interco_tgt_sel_remapped;
 
   tcdm_master_resp_t   [NumCoresPerTile-1:0] remote_resp_interco;
   logic                [NumCoresPerTile-1:0] remote_resp_interco_valid;
   logic                [NumCoresPerTile-1:0] remote_resp_interco_ready;
 
 
-  logic                [NumCoresPerTile-1:0] remote_req_interco_valid_mask_local;
-  logic                [NumCoresPerTile-1:0][$clog2(NumRemotePortsPerTile-1)-1:0] remote_req_interco_tgt_sel_mask_local;
-  logic                [NumCoresPerTile-1:0] remote_req_interco_tgt_sel_mask_local_vld;
-  remote_ports_index_t [NumCoresPerTile-1:0] remote_req_interco_tgt_sel_shift_local;
 
   logic                [NumCoresPerTile-1:0] remote_req_interco_to_xbar_valid;
   logic                [NumCoresPerTile-1:0] remote_req_interco_to_xbar_valid_q;
   logic                [NumCoresPerTile-1:0] remote_req_interco_to_xbar_ready;
-
-
-  for(genvar c = 0; c < NumCoresPerTile; c++) begin: gen_remote_req_interco_handle_local
-    assign group_id_is_local[c] = tgt_group_id[c] == group_id;
-
-    assign remote_req_interco_valid_mask_local[c] = group_id_is_local[c] ? 0 : remote_req_interco_valid[c];
-
-
-    assign remote_req_interco_tgt_sel_shift_local[c] = 
-    {{($bits(remote_ports_index_t) - $clog2(NumRemotePortsPerTile-1)){1'b0}}, remote_req_interco_tgt_sel_mask_local[c]} + 1;
-
-    // assign remote_req_interco_to_xbar_valid[c] = group_id_is_local[c] ? remote_req_interco_valid[c] :
-    //                                              remote_req_interco_tgt_sel_mask_local_vld[c];
-    assign remote_req_interco_to_xbar_valid[c] = remote_req_interco_valid[c];
-    // assign remote_req_interco_to_xbar_ready[c] = group_id_is_local[c] ? remote_req_interco_ready[c] :
-    //                                              remote_req_interco_tgt_sel_mask_local_vld[c] & remote_req_interco_ready[c];
-    assign remote_req_interco_to_xbar_ready[c] = remote_req_interco_ready[c];
-
-    assign remote_req_interco_hsk[c] = remote_req_interco_to_xbar_valid[c] & remote_req_interco_to_xbar_ready[c];
-    assign remote_req_interco_tgt_sel_q_update[c] = (remote_req_interco_hsk_q[c] & remote_req_interco_to_xbar_valid[c]) |
-                                                    (~remote_req_interco_to_xbar_valid_q[c] & remote_req_interco_to_xbar_valid[c]);
-
-    `FF(remote_req_interco_hsk_q[c], remote_req_interco_hsk[c], '0, clk_i, rst_ni);
-    `FF(remote_req_interco_to_xbar_valid_q[c], remote_req_interco_to_xbar_valid[c], '0, clk_i, rst_ni);
-    `FFLARN(remote_req_interco_tgt_sel_q[c], remote_req_interco_tgt_sel[c], remote_req_interco_tgt_sel_q_update[c], '0, clk_i, rst_ni);
-  end: gen_remote_req_interco_handle_local
-
-
-  logic [$clog2(NumCoresPerTile)-1:0] priority_d, priority_q;
-  assign priority_d = (priority_q == (NumCoresPerTile-1)) ? '0 : priority_q + 1;
-  `FF(priority_q, priority_d, '0, clk_i, rst_ni);
-
-`ifdef DYNAMIC_PORT_ALLOC
-  selector #(
-    .InNum    (NumCoresPerTile),
-    .OutNum   (NumRemotePortsPerTile-1)
-  ) i_selector (
-    .req_vector_i             (remote_req_interco_valid_mask_local),
-    .priority_i               (priority_q               ),
-    .sel_inport_idx_o         (                         ),
-    .asn_outport_idx_o        (remote_req_interco_tgt_sel_mask_local),
-    .asn_outport_vld_o        (remote_req_interco_tgt_sel_mask_local_vld)
-  );
-`else
-  assign remote_req_interco_tgt_sel_mask_local = '0;
-  assign remote_req_interco_tgt_sel_mask_local_vld = '0;
-`endif
 
   stream_xbar #(
     .NumInp   (NumCoresPerTile           ),
@@ -864,7 +773,7 @@ module mempool_tile
 
   logic             [NumCoresPerTile-1:0] local_req_interco_valid;
   logic             [NumCoresPerTile-1:0] local_req_interco_ready;
-  // tcdm_slave_req_t  [NumCoresPerTile-1:0] local_req_interco_payload;
+  tcdm_slave_req_t  [NumCoresPerTile-1:0] local_req_interco_payload;
   logic             [NumCoresPerTile-1:0] local_resp_interco_valid;
   logic             [NumCoresPerTile-1:0] local_resp_interco_ready;
   tcdm_slave_resp_t [NumCoresPerTile-1:0] local_resp_interco_payload;
@@ -922,6 +831,36 @@ module mempool_tile
     .idx_o  (/* Unused */                                            )
   );
 
+  /********************
+   *   ID Remapping   *
+   ********************/
+  mempool_tile_id_remapper #()
+  i_mempool_tile_id_remapper
+  (
+    .clk_i              (clk_i      ),
+    .rst_ni             (rst_ni     ),
+
+    .group_id_i         (group_id   ),
+
+    .tcdm_dma_req_i           (tcdm_dma_req_i     ),
+    .tcdm_slave_req_i         (tcdm_slave_req_i   ),
+    .local_req_interco_payload_i  (local_req_interco_payload),
+
+    .remote_req_interco_valid_i (remote_req_interco_valid   ),
+    .remote_req_interco_ready_i (remote_req_interco_ready   ),
+    .remote_req_interco_tgt_sel_i (remote_req_interco_tgt_sel),
+
+    .prescramble_tcdm_req_tgt_addr_i  (prescramble_tcdm_req_tgt_addr),
+
+    .tcdm_dma_req_remapped_o    (tcdm_dma_req_remapped),
+    .tcdm_slave_req_remapped_o  (tcdm_slave_req_remapped),
+    .local_req_interco_payload_remapped_o  (local_req_interco_payload_remapped),
+
+    .remote_req_interco_to_xbar_valid_o (remote_req_interco_to_xbar_valid),
+    .remote_req_interco_to_xbar_ready_o (remote_req_interco_to_xbar_ready),
+    .remote_req_interco_tgt_sel_o (remote_req_interco_tgt_sel_remapped)
+  );
+
   /*******************
    *   Core De/mux   *
    *******************/
@@ -984,13 +923,8 @@ module mempool_tile
         // Output port depends on both the target and initiator group
         // If the target group is the same as the initiator group, the target is the local Group, through port 0
         // Otherwise, the target is a remote group, through port 1 to NumRemotePortsPerTile, used in a round-robin fashion by modulus
-        // group_id_t tgt_group_id;
         assign tgt_group_id[c] = prescramble_tcdm_req_tgt_addr[c][ByteOffset + $clog2(NumBanksPerTile) + $clog2(NumTilesPerGroup) +: $clog2(NumGroups)];
-        assign remote_req_interco_tgt_sel[c] = group_id_is_local[c] ? 0 : (1 + (c % (NumRemotePortsPerTile - 1)));
-        // assign remote_req_interco_tgt_sel[c] = group_id_is_local[c] ? 0 :
-        //                                       //  ~remote_req_interco_tgt_sel_q_update[c] ? remote_req_interco_tgt_sel_q[c] :
-        //                                        (remote_req_interco_to_xbar_valid[c] ? remote_req_interco_tgt_sel_shift_local[c] :
-        //                                        (1 + (c % (NumRemotePortsPerTile - 1))));
+        assign remote_req_interco_tgt_sel[c] = remote_req_interco_tgt_sel_remapped[c];
         assign remote_req_interco[c].tgt_group_id = tgt_group_id[c];
       end