treewide: Add Saxon SoC USB 1.1 (OHCI) controller #1540
reviewdog [verible-verilog-lint] report
reported by reviewdog 🐶
Findings (711)
hw/future/UsbOhciAxi4.v|258 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|259 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|260 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|261 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|262 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|263 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|264 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|265 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|266 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|267 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|268 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|269 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|270 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|271 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|272 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|273 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|274 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|275 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|276 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|277 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|278 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|279 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|280 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|281 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|282 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|283 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|284 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|285 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|286 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|287 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|288 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|289 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|290 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|291 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|292 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|293 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|296 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|297 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|298 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|299 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|300 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|301 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|302 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|303 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|304 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|305 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|306 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|307 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|308 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|309 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|310 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|311 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|312 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|313 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|314 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|315 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|316 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|317 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|318 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|319 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|320 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|321 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|322 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|323 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|324 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|325 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|326 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|327 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|328 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|329 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|330 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|331 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|332 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|333 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|334 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|335 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|336 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|337 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|338 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|383 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|384 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|385 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|386 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|387 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|388 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|389 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|390 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|391 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|392 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|393 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|394 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|395 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|396 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|397 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|398 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|399 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|400 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|401 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|402 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|403 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|404 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|405 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|406 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|407 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|408 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|409 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|410 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|411 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|412 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|413 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|414 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|415 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|416 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|417 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|418 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|419 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|420 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|421 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|422 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|423 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|424 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|425 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|426 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|427 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|428 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|429 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|430 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|431 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|432 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|433 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|434 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|435 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|436 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|437 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|438 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|439 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|440 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|441 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|442 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|443 col 101| Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|549 col 101| Line length exceeds max: 100; is: 129 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|550 col 101| Line length exceeds max: 100; is: 112 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|561 col 101| Line length exceeds max: 100; is: 116 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|899 col 3| Use 'always_comb' instead of 'always @*'. [Style: combinational-logic] [always-comb]
hw/future/UsbOhciAxi4.v|908 col 101| Line length exceeds max: 100; is: 105 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|909 col 101| Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|916 col 101| Line length exceeds max: 100; is: 103 [Style: line-length] [line-length]
hw/future/UsbOhciAxi4.v|995 col 14| Explicitly define a storage type for every parameter and localparam, (UsbOhciAxi4_txShared_frame_enumDef_BOOT). [Style: constants] [explicit-parameter-storage-type]
hw/future/UsbOhciAxi4.v|996 col 14| Explicitly define a storage type for every parameter and localparam, (UsbOhciAxi4_txShared_frame_enumDef_IDLE). [Style: constants] [explicit-parameter-storage-type]
hw/future/UsbOhciAxi4.v|997 col 14| Explicitly define a storage type for every parameter and localparam, (UsbOhciAxi4_txShared_frame_enumDef_TAKE_LINE). [Style: constants] [explicit-parameter-storage-type]
... (Too many findings. Dropped some findings)
Filtered Findings (0)
Annotations
Check warning on line 258 in hw/future/UsbOhciAxi4.v
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/future/UsbOhciAxi4.v#L258
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]" location:{path:"hw/future/UsbOhciAxi4.v" range:{start:{line:258 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 259 in hw/future/UsbOhciAxi4.v
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/future/UsbOhciAxi4.v#L259
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]" location:{path:"hw/future/UsbOhciAxi4.v" range:{start:{line:259 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 260 in hw/future/UsbOhciAxi4.v
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/future/UsbOhciAxi4.v#L260
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]" location:{path:"hw/future/UsbOhciAxi4.v" range:{start:{line:260 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 261 in hw/future/UsbOhciAxi4.v
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/future/UsbOhciAxi4.v#L261
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]" location:{path:"hw/future/UsbOhciAxi4.v" range:{start:{line:261 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 262 in hw/future/UsbOhciAxi4.v
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/future/UsbOhciAxi4.v#L262
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]" location:{path:"hw/future/UsbOhciAxi4.v" range:{start:{line:262 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 263 in hw/future/UsbOhciAxi4.v
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/future/UsbOhciAxi4.v#L263
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]" location:{path:"hw/future/UsbOhciAxi4.v" range:{start:{line:263 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 264 in hw/future/UsbOhciAxi4.v
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/future/UsbOhciAxi4.v#L264
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]" location:{path:"hw/future/UsbOhciAxi4.v" range:{start:{line:264 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 265 in hw/future/UsbOhciAxi4.v
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/future/UsbOhciAxi4.v#L265
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]" location:{path:"hw/future/UsbOhciAxi4.v" range:{start:{line:265 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 266 in hw/future/UsbOhciAxi4.v
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/future/UsbOhciAxi4.v#L266
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]" location:{path:"hw/future/UsbOhciAxi4.v" range:{start:{line:266 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 267 in hw/future/UsbOhciAxi4.v
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/future/UsbOhciAxi4.v#L267
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]" location:{path:"hw/future/UsbOhciAxi4.v" range:{start:{line:267 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 268 in hw/future/UsbOhciAxi4.v
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/future/UsbOhciAxi4.v#L268
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]" location:{path:"hw/future/UsbOhciAxi4.v" range:{start:{line:268 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 269 in hw/future/UsbOhciAxi4.v
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/future/UsbOhciAxi4.v#L269
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]" location:{path:"hw/future/UsbOhciAxi4.v" range:{start:{line:269 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 270 in hw/future/UsbOhciAxi4.v
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/future/UsbOhciAxi4.v#L270
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]" location:{path:"hw/future/UsbOhciAxi4.v" range:{start:{line:270 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 271 in hw/future/UsbOhciAxi4.v
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/future/UsbOhciAxi4.v#L271
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]" location:{path:"hw/future/UsbOhciAxi4.v" range:{start:{line:271 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 272 in hw/future/UsbOhciAxi4.v
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/future/UsbOhciAxi4.v#L272
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]" location:{path:"hw/future/UsbOhciAxi4.v" range:{start:{line:272 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 273 in hw/future/UsbOhciAxi4.v
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/future/UsbOhciAxi4.v#L273
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]" location:{path:"hw/future/UsbOhciAxi4.v" range:{start:{line:273 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 274 in hw/future/UsbOhciAxi4.v
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/future/UsbOhciAxi4.v#L274
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]" location:{path:"hw/future/UsbOhciAxi4.v" range:{start:{line:274 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 275 in hw/future/UsbOhciAxi4.v
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/future/UsbOhciAxi4.v#L275
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]" location:{path:"hw/future/UsbOhciAxi4.v" range:{start:{line:275 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 276 in hw/future/UsbOhciAxi4.v
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/future/UsbOhciAxi4.v#L276
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]" location:{path:"hw/future/UsbOhciAxi4.v" range:{start:{line:276 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 277 in hw/future/UsbOhciAxi4.v
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/future/UsbOhciAxi4.v#L277
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]" location:{path:"hw/future/UsbOhciAxi4.v" range:{start:{line:277 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 278 in hw/future/UsbOhciAxi4.v
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/future/UsbOhciAxi4.v#L278
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]" location:{path:"hw/future/UsbOhciAxi4.v" range:{start:{line:278 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 279 in hw/future/UsbOhciAxi4.v
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/future/UsbOhciAxi4.v#L279
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]" location:{path:"hw/future/UsbOhciAxi4.v" range:{start:{line:279 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 280 in hw/future/UsbOhciAxi4.v
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/future/UsbOhciAxi4.v#L280
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]" location:{path:"hw/future/UsbOhciAxi4.v" range:{start:{line:280 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 281 in hw/future/UsbOhciAxi4.v
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/future/UsbOhciAxi4.v#L281
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]" location:{path:"hw/future/UsbOhciAxi4.v" range:{start:{line:281 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 282 in hw/future/UsbOhciAxi4.v
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/future/UsbOhciAxi4.v#L282
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]" location:{path:"hw/future/UsbOhciAxi4.v" range:{start:{line:282 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}