Wrap cores in idle HMR unit. #1506
reviewdog [verible-verilog-lint] report
reported by reviewdog 🐶
Findings (7)
hw/cva6_wrap.sv|35 col 101| Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]
hw/cva6_wrap.sv|37 col 101| Line length exceeds max: 100; is: 119 [Style: line-length] [line-length]
hw/cva6_wrap.sv|38 col 101| Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]
hw/cva6_wrap.sv|39 col 101| Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
hw/cva6_wrap.sv|40 col 101| Line length exceeds max: 100; is: 116 [Style: line-length] [line-length]
hw/cva6_wrap.sv|41 col 101| Line length exceeds max: 100; is: 112 [Style: line-length] [line-length]
hw/cva6_wrap.sv|42 col 101| Line length exceeds max: 100; is: 116 [Style: line-length] [line-length]
Filtered Findings (0)
Annotations
Check warning on line 35 in hw/cva6_wrap.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/cva6_wrap.sv#L35
Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]" location:{path:"hw/cva6_wrap.sv" range:{start:{line:35 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 37 in hw/cva6_wrap.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/cva6_wrap.sv#L37
Line length exceeds max: 100; is: 119 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 119 [Style: line-length] [line-length]" location:{path:"hw/cva6_wrap.sv" range:{start:{line:37 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 38 in hw/cva6_wrap.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/cva6_wrap.sv#L38
Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]" location:{path:"hw/cva6_wrap.sv" range:{start:{line:38 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 39 in hw/cva6_wrap.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/cva6_wrap.sv#L39
Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]" location:{path:"hw/cva6_wrap.sv" range:{start:{line:39 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 40 in hw/cva6_wrap.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/cva6_wrap.sv#L40
Line length exceeds max: 100; is: 116 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 116 [Style: line-length] [line-length]" location:{path:"hw/cva6_wrap.sv" range:{start:{line:40 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 41 in hw/cva6_wrap.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/cva6_wrap.sv#L41
Line length exceeds max: 100; is: 112 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 112 [Style: line-length] [line-length]" location:{path:"hw/cva6_wrap.sv" range:{start:{line:41 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 42 in hw/cva6_wrap.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/cva6_wrap.sv#L42
Line length exceeds max: 100; is: 116 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 116 [Style: line-length] [line-length]" location:{path:"hw/cva6_wrap.sv" range:{start:{line:42 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}