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Reworked FPGA flow for multi board / flavor support #94
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…d Vivado IP simulation flow fpga: Added ddr4 and vcu128 flow, added draft of Vivado IP simulation flow fpga: Added VIOs Connect VIO-generated reset signal to dram wrapper fpga: Support of zcu102 fpga: zcu102.xdc constraint file added fpga: zcu102 changed phy and added firsts constraints fpga: Switching to clk_wiz and xilinx.mk fpga: Testing ddr4 fpga: Start working on SPI driver Co-Authored-By: Yann Picod <[email protected]> fpga: SD card test fpga: Rolled-back SD fpga: Add vcu128 ci fpga: Debug new CI fpga: Adding artifacts management fpga: Added ID serializer in dram_wrapper and changed a few xdc constraints fpga: Correcting artifacts mngmt and applied new constraints to genesys2 fpga: Corrected vivado sim script fpga: Last review updates fpga: Last review updates 2 fpga: Updated artifact management to take select only useful envvar fpga: Update cva6-sdk, add openocd configs, and update docs fpga: Use https for cva6-sdk fpga: Removed a few phonies/variable defined targets fpga: Moved to flavoured flow
CyrilKoe
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Reworked FPGA flow and added VCU128 support
Reworked FPGA flow for multi board / flavor support
Feb 12, 2024
@paulsc96 removed VCU128 and sim folder. Todo align CI |
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@paulsc96 vcu128 removed, this PR should be merged if possible, CI passes, changing docs now |
Since #105 is converging, closing in favor of that (keeping the branch of course) |
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This PR goes with the MR 11
Changes :
CI status :