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treewide: Update AXI-RT, extend tests #77

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Sep 26, 2023
Merged

treewide: Update AXI-RT, extend tests #77

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8 changes: 4 additions & 4 deletions Bender.lock
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Original file line number Diff line number Diff line change
Expand Up @@ -44,8 +44,8 @@ packages:
- common_cells
- common_verification
axi_rt:
revision: b243310dd33b31e4e2ca5229aac20df25cfc45d5
version: 0.0.0-alpha
revision: a9a5b3e91fe017da70c33b7e750b1a9eb35f31ee
version: 0.0.0-alpha.3
source:
Git: https://github.com/pulp-platform/axi_rt.git
dependencies:
Expand Down Expand Up @@ -78,8 +78,8 @@ packages:
- common_cells
- register_interface
common_cells:
revision: 53b0b58af2db5bd3c850a7038fae170ed78326bb
version: 1.31.1
revision: 2bd027cb87eaa9bf7d17196ec5f69864b35b630f
version: 1.32.0
source:
Git: https://github.com/pulp-platform/common_cells.git
dependencies:
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4 changes: 2 additions & 2 deletions Bender.yml
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Expand Up @@ -16,11 +16,11 @@ dependencies:
axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.0 }
axi_llc: { git: "https://github.com/pulp-platform/axi_llc.git", version: 0.2.1 }
axi_riscv_atomics: { git: "https://github.com/pulp-platform/axi_riscv_atomics.git", version: 0.8.1 }
axi_rt: { git: "https://github.com/pulp-platform/axi_rt.git", version: 0.0.0-alpha }
axi_rt: { git: "https://github.com/pulp-platform/axi_rt.git", version: 0.0.0-alpha.3 }
axi_vga: { git: "https://github.com/pulp-platform/axi_vga.git", version: 0.1.1 }
clic: { git: "https://github.com/pulp-platform/clic.git", version: 2.0.0 }
clint: { git: "https://github.com/pulp-platform/clint.git", version: 0.2.0 }
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 }
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.32.0 }
common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.0 }
cva6: { git: "https://github.com/pulp-platform/cva6.git", rev: pulp-v0.4.3 }
iDMA: { git: "https://github.com/pulp-platform/iDMA.git", version: 0.5.1 }
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2 changes: 1 addition & 1 deletion cheshire.mk
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Expand Up @@ -53,7 +53,7 @@ chs-clean-deps:
######################

CHS_NONFREE_REMOTE ?= [email protected]:pulp-restricted/cheshire-nonfree.git
CHS_NONFREE_COMMIT ?= 900e294
CHS_NONFREE_COMMIT ?= dafd3c1

chs-nonfree-init:
git clone $(CHS_NONFREE_REMOTE) $(CHS_ROOT)/nonfree
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62 changes: 62 additions & 0 deletions sw/tests/axirt_budget.c
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@@ -0,0 +1,62 @@
// Copyright 2023 ETH Zurich and University of Bologna.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Thomas Benz <[email protected]>
//
// Validate the budget functionality of AXI RT

#include "axirt.h"
#include "dif/dma.h"
#include "regs/axi_rt.h"
#include "params.h"
#include "util.h"

// transfer
#define SIZE_BYTES 256
#define SRC_STRIDE 0
#define DST_STRIDE 0
#define NUM_REPS 8
#define SRC_ADDR 0x0000000010000000
#define DST_ADDR 0x0000000080000000

#define TOTAL_SIZE (SIZE_BYTES * NUM_REPS)

int main(void) {

// enable and configure axi rt with fragmentation of 8 beats
__axirt_claim(1, 1);
__axirt_set_len_limit_group(7, 0);

// configure CVA6
__axirt_set_region(0, 0xffffffff, 0, 0);
__axirt_set_region(0x100000000, 0xffffffffffffffff, 1, 0);
__axirt_set_budget(0x10000000, 0, 0);
__axirt_set_budget(0x10000000, 1, 0);
__axirt_set_period(0x10000000, 0, 0);
__axirt_set_period(0x10000000, 1, 0);

// configure DMA
__axirt_set_region(0, 0xffffffff, 0, 2);
__axirt_set_region(0x100000000, 0xffffffffffffffff, 1, 2);
__axirt_set_budget(0x10000000, 0, 2);
__axirt_set_budget(0x10000000, 1, 2);
__axirt_set_period(0x10000000, 0, 2);
__axirt_set_period(0x10000000, 1, 2);

// enable RT unit for DMA and CVA6
__axirt_enable(0x5);

// launch DMA transfer
sys_dma_2d_blk_memcpy(DST_ADDR, SRC_ADDR, SIZE_BYTES, DST_STRIDE, SRC_STRIDE, NUM_REPS);

// read budget registers and compare
volatile uint32_t read_budget = *reg32(&__base_axirt, AXI_RT_READ_BUDGET_LEFT_2_REG_OFFSET);
volatile uint32_t write_budget = *reg32(&__base_axirt, AXI_RT_WRITE_BUDGET_LEFT_2_REG_OFFSET);

// check
volatile uint8_t difference = (TOTAL_SIZE - read_budget) + (TOTAL_SIZE - write_budget);
volatile uint8_t mismatch = read_budget != write_budget;

return mismatch | (difference << 1);
}
30 changes: 20 additions & 10 deletions sw/tests/helloaxirt.c → sw/tests/axirt_hello.c
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Expand Up @@ -23,16 +23,26 @@ int main(void) {

// enable and configure axi rt
__axirt_claim(1, 1);
for (int m = 0; m < AXI_RT_PARAM_NUM_MRG; m++) {
__axirt_set_len_limit(8, m);
__axirt_set_region(0, 0xffffffff, 0, m);
__axirt_set_region(0x100000000, 0xffffffffffffffff, 1, m);
__axirt_set_budget(0x10000000, 0, m);
__axirt_set_budget(0x10000000, 1, m);
__axirt_set_period(0x10000000, 0, m);
__axirt_set_period(0x10000000, 1, m);
}
__axirt_enable(0xffffffff);
__axirt_set_len_limit_group(2, 0);

// configure CVA6
__axirt_set_region(0, 0xffffffff, 0, 0);
__axirt_set_region(0x100000000, 0xffffffffffffffff, 1, 0);
__axirt_set_budget(8, 0, 0);
__axirt_set_budget(8, 1, 0);
__axirt_set_period(100, 0, 0);
__axirt_set_period(100, 1, 0);

// configure DMA
__axirt_set_region(0, 0xffffffff, 0, 2);
__axirt_set_region(0x100000000, 0xffffffffffffffff, 1, 2);
__axirt_set_budget(0x10000000, 0, 2);
__axirt_set_budget(0x10000000, 1, 2);
__axirt_set_period(0x10000000, 0, 2);
__axirt_set_period(0x10000000, 1, 2);

// enable RT unit for DMA and CVA6
__axirt_enable(0x5);

// configure uart and write msg
uart_init(&__base_uart, reset_freq, 115200);
Expand Down
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