Add VCU118 support to ara-pulpv1-os

Bender.lock

@@ -15,10 +15,10 @@ packages:
     - apb
     - register_interface
   ara:
-    revision: 09142d01d3fd5dedc3f962fe67ac63be999e6ad2
+    revision: c3355df5ecf742c4e7a92a428cb7467045b5b163
     version: null
     source:
-      Git: https://github.com/mp-17/ara.git
+      Git: https://github.com/pulp-platform/ara.git
     dependencies:
     - apb
     - axi
@@ -103,10 +103,10 @@ packages:
       Git: https://github.com/pulp-platform/common_verification.git
     dependencies: []
   cva6:
-    revision: 2240a61da2cdccf38e2aa932a19180d6faa7a31d
+    revision: 5614fc9ceeae6db3851e8c721de868355db9476b
     version: null
     source:
-      Git: https://github.com/mp-17/cva6.git
+      Git: https://github.com/pulp-platform/cva6.git
     dependencies:
     - axi
     - common_cells

Bender.yml

@@ -22,8 +22,8 @@ dependencies:
   clint:                    { git: "https://github.com/pulp-platform/clint.git",                  version: 0.2.0  }
   common_cells:             { git: "https://github.com/pulp-platform/common_cells.git",           version: 1.33.0 }
   common_verification:      { git: "https://github.com/pulp-platform/common_verification.git",    version: 0.2.0  }
-  cva6:                     { git: "https://github.com/mp-17/cva6.git",                           rev: mp/pulp-v1 }
-  ara:                      { git: "https://github.com/mp-17/ara.git",                            rev: mp/cva6-pulpv1/rebase }
+  cva6:                     { git: "https://github.com/pulp-platform/cva6.git",                   rev: mp/pulp-v1-araOS }
+  ara:                      { git: "https://github.com/pulp-platform/ara.git",                    rev: mp/pulp-v1-os-fpga }
   iDMA:                     { git: "https://github.com/pulp-platform/iDMA.git",                   version: 0.5.1  }
   irq_router:               { git: "https://github.com/pulp-platform/irq_router.git",             version: 0.0.1-beta.1 }
   opentitan_peripherals:    { git: "https://github.com/pulp-platform/opentitan_peripherals.git",  version: 0.4.0  }

hw/cheshire_soc.sv

@@ -548,8 +548,8 @@ module cheshire_soc import cheshire_pkg::*; #(
   // TODO: Implement X interface support
 
   // Accelerator ports
-  acc_pkg::accelerator_req_t  acc_req;
-  acc_pkg::accelerator_resp_t acc_resp;
+  acc_pkg::cva6_to_acc_t acc_req;
+  acc_pkg::acc_to_cva6_t acc_resp;
 
   // CVA6-Ara memory consistency
   logic                     acc_cons_en;
@@ -558,13 +558,13 @@ module cheshire_soc import cheshire_pkg::*; #(
   logic                     inval_ready;
 
   // Pack invalidation interface into acc interface
-  acc_pkg::accelerator_resp_t acc_resp_pack;
+  acc_pkg::acc_to_cva6_t acc_resp_pack;
   always_comb begin : pack_inval
-    acc_resp_pack             = acc_resp;
-    acc_resp_pack.inval_valid = inval_valid;
-    acc_resp_pack.inval_addr  = inval_addr;
-    inval_ready               = acc_req.inval_ready;
-    acc_cons_en               = acc_req.acc_cons_en;
+    acc_resp_pack                      = acc_resp;
+    acc_resp_pack.acc_resp.inval_valid = inval_valid;
+    acc_resp_pack.acc_resp.inval_addr  = inval_addr;
+    inval_ready                        = acc_req.acc_req.inval_ready;
+    acc_cons_en                        = acc_req.acc_req.acc_cons_en;
   end
 
   `CHESHIRE_TYPEDEF_AXI_CT(axi_cva6, addr_t, cva6_id_t, axi_data_t, axi_strb_t, axi_user_t)
@@ -617,8 +617,8 @@ module cheshire_soc import cheshire_pkg::*; #(
       .axi_w_chan_t   ( axi_cva6_w_chan_t  ),
       .b_chan_t       ( axi_cva6_b_chan_t  ),
       .r_chan_t       ( axi_cva6_r_chan_t  ),
-      .cvxif_req_t    ( acc_pkg::accelerator_req_t  ),
-      .cvxif_resp_t   ( acc_pkg::accelerator_resp_t ),
+      .cvxif_req_t    ( acc_pkg::cva6_to_acc_t ),
+      .cvxif_resp_t   ( acc_pkg::acc_to_cva6_t ),
       .noc_req_t      ( axi_cva6_req_t ),
       .noc_resp_t     ( axi_cva6_rsp_t )
     ) i_core_cva6 (

sw/boot/cheshire.dtsi

@@ -30,7 +30,7 @@
       status = "okay";
       compatible = "eth,ariane", "riscv";
       clock-frequency = <50000000>; // 50 MHz
-      riscv,isa = "rv64imafdc";
+      riscv,isa = "rv64imafdcv";
       mmu-type = "riscv,sv39";
       tlb-split;
       reg = <0>;

sw/boot/cheshire.vcu118.dts

@@ -0,0 +1,20 @@
+// Copyright 2024 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Cyril Koenig <[email protected]>
+// Mojtaba Rostami <[email protected]>
+
+/include/ "cheshire.dtsi"
+
+&spi {
+  boot-with = <0>;
+  mmc@0 {
+    compatible = "mmc-spi-slot";
+    reg = <0>; // CS
+    spi-max-frequency = <25000000>;
+    voltage-ranges = <3300 3300>;
+    clock-frequency = <1000000>;
+    disable-wp;
+  };
+};

target/xilinx/constraints/vcu118.xdc

@@ -0,0 +1,199 @@
+# Copyright 2022 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+#
+# Nicole Narr <[email protected]>
+# Christopher Reinwardt <[email protected]>
+# Cyril Koenig <[email protected]>
+# Paul Scheffler <[email protected]>
+
+#############
+# Sys Clock #
+#############
+
+# 125 MHz input clock
+set_property -dict {LOC AY24 IOSTANDARD LVDS} [get_ports sys_clk_p]
+set_property -dict {LOC AY23 IOSTANDARD LVDS} [get_ports sys_clk_n]
+create_clock -period 8.000 -name clk_125mhz [get_ports sys_clk_p]
+
+# SoC clock is generated by clock wizard and its constraints
+set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets i_clkwiz/inst/clk_50]
+
+
+#######
+# MIG #
+#######
+
+# Dram axi clock : 333 MHz (defined by MIG constraints)
+
+# False-path incoming reset
+set_false_path -setup -hold -through [get_pins i_dram_wrapper/i_dram/c0_ddr4_aresetn]
+
+# Constrain outgoing reset
+set_false_path -hold -through [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst]
+set_max_delay -through [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst] 3.000
+
+# Limit delay across DRAM CDC (hold already false-pathed)
+# tclint-disable line-length
+set_max_delay -datapath_only -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*i_sync/reg*/D] 3.000
+set_max_delay -datapath_only -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] 3.000
+# tclint-enable line-length
+
+###############
+# Assign Pins #
+###############
+
+# tclint-disable line-length, spacing
+
+set_property PACKAGE_PIN AW25 [get_ports uart_rx_i]
+set_property IOSTANDARD LVCMOS18 [get_ports uart_rx_i]
+set_property PACKAGE_PIN BB21 [get_ports uart_tx_o]
+set_property IOSTANDARD LVCMOS18 [get_ports uart_tx_o]
+
+
+# Active high reset (GPIO_SW_N)
+set_property PACKAGE_PIN BB24 [get_ports sys_reset]
+set_property IOSTANDARD LVCMOS18 [get_ports sys_reset]
+
+# tclint-enable line-length, spacing
+
+# SD Card
+set_property -dict {PACKAGE_PIN AT15 IOSTANDARD LVCMOS12} [get_ports sd_cd_i]
+set_property -dict {PACKAGE_PIN AY15 IOSTANDARD LVCMOS12} [get_ports sd_cmd_o]
+set_property -dict {PACKAGE_PIN AW15 IOSTANDARD LVCMOS12} [get_ports {sd_d_io[0]}]
+set_property -dict {PACKAGE_PIN AV16 IOSTANDARD LVCMOS12} [get_ports {sd_d_io[1]}]
+set_property -dict {PACKAGE_PIN AU16 IOSTANDARD LVCMOS12} [get_ports {sd_d_io[2]}]
+set_property -dict {PACKAGE_PIN AY14 IOSTANDARD LVCMOS12} [get_ports {sd_d_io[3]}]
+set_property -dict {PACKAGE_PIN AV15 IOSTANDARD LVCMOS12} [get_ports sd_sclk_o]
+
+
+## DDR4
+
+set_property IOSTANDARD DIFF_SSTL12 [get_ports c0_sys_clk_n]
+set_property PACKAGE_PIN E12 [get_ports c0_sys_clk_p]
+set_property PACKAGE_PIN D12 [get_ports c0_sys_clk_n]
+set_property IOSTANDARD DIFF_SSTL12 [get_ports c0_sys_clk_p]
+
+set_property PACKAGE_PIN E13 [get_ports c0_ddr4_act_n]
+set_property PACKAGE_PIN D14 [get_ports {c0_ddr4_adr[0]}]
+set_property PACKAGE_PIN C12 [get_ports {c0_ddr4_adr[10]}]
+set_property PACKAGE_PIN B13 [get_ports {c0_ddr4_adr[11]}]
+set_property PACKAGE_PIN C13 [get_ports {c0_ddr4_adr[12]}]
+set_property PACKAGE_PIN D15 [get_ports {c0_ddr4_adr[13]}]
+set_property PACKAGE_PIN H14 [get_ports {c0_ddr4_adr[14]}]
+set_property PACKAGE_PIN H15 [get_ports {c0_ddr4_adr[15]}]
+set_property PACKAGE_PIN F15 [get_ports {c0_ddr4_adr[16]}]
+set_property PACKAGE_PIN B15 [get_ports {c0_ddr4_adr[1]}]
+set_property PACKAGE_PIN B16 [get_ports {c0_ddr4_adr[2]}]
+set_property PACKAGE_PIN C14 [get_ports {c0_ddr4_adr[3]}]
+set_property PACKAGE_PIN C15 [get_ports {c0_ddr4_adr[4]}]
+set_property PACKAGE_PIN A13 [get_ports {c0_ddr4_adr[5]}]
+set_property PACKAGE_PIN A14 [get_ports {c0_ddr4_adr[6]}]
+set_property PACKAGE_PIN A15 [get_ports {c0_ddr4_adr[7]}]
+set_property PACKAGE_PIN A16 [get_ports {c0_ddr4_adr[8]}]
+set_property PACKAGE_PIN B12 [get_ports {c0_ddr4_adr[9]}]
+set_property PACKAGE_PIN G15 [get_ports {c0_ddr4_ba[0]}]
+set_property PACKAGE_PIN G13 [get_ports {c0_ddr4_ba[1]}]
+set_property PACKAGE_PIN H13 [get_ports {c0_ddr4_bg[0]}]
+set_property PACKAGE_PIN F14 [get_ports {c0_ddr4_ck_t[0]}]
+set_property PACKAGE_PIN E14 [get_ports {c0_ddr4_ck_c[0]}]
+set_property PACKAGE_PIN A10 [get_ports {c0_ddr4_cke[0]}]
+set_property PACKAGE_PIN F13 [get_ports {c0_ddr4_cs_n[0]}]
+set_property PACKAGE_PIN G11 [get_ports {c0_ddr4_dm_dbi_n[0]}]
+set_property PACKAGE_PIN R18 [get_ports {c0_ddr4_dm_dbi_n[1]}]
+set_property PACKAGE_PIN K17 [get_ports {c0_ddr4_dm_dbi_n[2]}]
+set_property PACKAGE_PIN G18 [get_ports {c0_ddr4_dm_dbi_n[3]}]
+set_property PACKAGE_PIN B18 [get_ports {c0_ddr4_dm_dbi_n[4]}]
+set_property PACKAGE_PIN P20 [get_ports {c0_ddr4_dm_dbi_n[5]}]
+set_property PACKAGE_PIN L23 [get_ports {c0_ddr4_dm_dbi_n[6]}]
+set_property PACKAGE_PIN G22 [get_ports {c0_ddr4_dm_dbi_n[7]}]
+
+set_property PACKAGE_PIN F11 [get_ports {c0_ddr4_dq[0]}]
+set_property PACKAGE_PIN M18 [get_ports {c0_ddr4_dq[10]}]
+set_property PACKAGE_PIN M17 [get_ports {c0_ddr4_dq[11]}]
+set_property PACKAGE_PIN N19 [get_ports {c0_ddr4_dq[12]}]
+set_property PACKAGE_PIN N18 [get_ports {c0_ddr4_dq[13]}]
+set_property PACKAGE_PIN N17 [get_ports {c0_ddr4_dq[14]}]
+set_property PACKAGE_PIN M16 [get_ports {c0_ddr4_dq[15]}]
+set_property PACKAGE_PIN L16 [get_ports {c0_ddr4_dq[16]}]
+set_property PACKAGE_PIN K16 [get_ports {c0_ddr4_dq[17]}]
+set_property PACKAGE_PIN L18 [get_ports {c0_ddr4_dq[18]}]
+set_property PACKAGE_PIN K18 [get_ports {c0_ddr4_dq[19]}]
+set_property PACKAGE_PIN E11 [get_ports {c0_ddr4_dq[1]}]
+set_property PACKAGE_PIN J17 [get_ports {c0_ddr4_dq[20]}]
+set_property PACKAGE_PIN H17 [get_ports {c0_ddr4_dq[21]}]
+set_property PACKAGE_PIN H19 [get_ports {c0_ddr4_dq[22]}]
+set_property PACKAGE_PIN H18 [get_ports {c0_ddr4_dq[23]}]
+set_property PACKAGE_PIN F19 [get_ports {c0_ddr4_dq[24]}]
+set_property PACKAGE_PIN F18 [get_ports {c0_ddr4_dq[25]}]
+set_property PACKAGE_PIN E19 [get_ports {c0_ddr4_dq[26]}]
+set_property PACKAGE_PIN E18 [get_ports {c0_ddr4_dq[27]}]
+set_property PACKAGE_PIN G20 [get_ports {c0_ddr4_dq[28]}]
+set_property PACKAGE_PIN F20 [get_ports {c0_ddr4_dq[29]}]
+set_property PACKAGE_PIN F10 [get_ports {c0_ddr4_dq[2]}]
+set_property PACKAGE_PIN E17 [get_ports {c0_ddr4_dq[30]}]
+set_property PACKAGE_PIN D16 [get_ports {c0_ddr4_dq[31]}]
+set_property PACKAGE_PIN D17 [get_ports {c0_ddr4_dq[32]}]
+set_property PACKAGE_PIN C17 [get_ports {c0_ddr4_dq[33]}]
+set_property PACKAGE_PIN C19 [get_ports {c0_ddr4_dq[34]}]
+set_property PACKAGE_PIN C18 [get_ports {c0_ddr4_dq[35]}]
+set_property PACKAGE_PIN D20 [get_ports {c0_ddr4_dq[36]}]
+set_property PACKAGE_PIN D19 [get_ports {c0_ddr4_dq[37]}]
+set_property PACKAGE_PIN C20 [get_ports {c0_ddr4_dq[38]}]
+set_property PACKAGE_PIN B20 [get_ports {c0_ddr4_dq[39]}]
+set_property PACKAGE_PIN F9 [get_ports {c0_ddr4_dq[3]}]
+set_property PACKAGE_PIN N23 [get_ports {c0_ddr4_dq[40]}]
+set_property PACKAGE_PIN M23 [get_ports {c0_ddr4_dq[41]}]
+set_property PACKAGE_PIN R21 [get_ports {c0_ddr4_dq[42]}]
+set_property PACKAGE_PIN P21 [get_ports {c0_ddr4_dq[43]}]
+set_property PACKAGE_PIN R22 [get_ports {c0_ddr4_dq[44]}]
+set_property PACKAGE_PIN P22 [get_ports {c0_ddr4_dq[45]}]
+set_property PACKAGE_PIN T23 [get_ports {c0_ddr4_dq[46]}]
+set_property PACKAGE_PIN R23 [get_ports {c0_ddr4_dq[47]}]
+set_property PACKAGE_PIN K24 [get_ports {c0_ddr4_dq[48]}]
+set_property PACKAGE_PIN J24 [get_ports {c0_ddr4_dq[49]}]
+set_property PACKAGE_PIN H12 [get_ports {c0_ddr4_dq[4]}]
+set_property PACKAGE_PIN M21 [get_ports {c0_ddr4_dq[50]}]
+set_property PACKAGE_PIN L21 [get_ports {c0_ddr4_dq[51]}]
+set_property PACKAGE_PIN K21 [get_ports {c0_ddr4_dq[52]}]
+set_property PACKAGE_PIN J21 [get_ports {c0_ddr4_dq[53]}]
+set_property PACKAGE_PIN K22 [get_ports {c0_ddr4_dq[54]}]
+set_property PACKAGE_PIN J22 [get_ports {c0_ddr4_dq[55]}]
+set_property PACKAGE_PIN H23 [get_ports {c0_ddr4_dq[56]}]
+set_property PACKAGE_PIN H22 [get_ports {c0_ddr4_dq[57]}]
+set_property PACKAGE_PIN E23 [get_ports {c0_ddr4_dq[58]}]
+set_property PACKAGE_PIN E22 [get_ports {c0_ddr4_dq[59]}]
+set_property PACKAGE_PIN G12 [get_ports {c0_ddr4_dq[5]}]
+set_property PACKAGE_PIN F21 [get_ports {c0_ddr4_dq[60]}]
+set_property PACKAGE_PIN E21 [get_ports {c0_ddr4_dq[61]}]
+set_property PACKAGE_PIN F24 [get_ports {c0_ddr4_dq[62]}]
+set_property PACKAGE_PIN F23 [get_ports {c0_ddr4_dq[63]}]
+
+set_property PACKAGE_PIN E9 [get_ports {c0_ddr4_dq[6]}]
+set_property PACKAGE_PIN D9 [get_ports {c0_ddr4_dq[7]}]
+set_property PACKAGE_PIN R19 [get_ports {c0_ddr4_dq[8]}]
+set_property PACKAGE_PIN P19 [get_ports {c0_ddr4_dq[9]}]
+
+set_property PACKAGE_PIN D11 [get_ports {c0_ddr4_dqs_t[0]}]
+set_property PACKAGE_PIN D10 [get_ports {c0_ddr4_dqs_c[0]}]
+set_property PACKAGE_PIN P17 [get_ports {c0_ddr4_dqs_t[1]}]
+set_property PACKAGE_PIN P16 [get_ports {c0_ddr4_dqs_c[1]}]
+set_property PACKAGE_PIN K19 [get_ports {c0_ddr4_dqs_t[2]}]
+set_property PACKAGE_PIN J19 [get_ports {c0_ddr4_dqs_c[2]}]
+set_property PACKAGE_PIN F16 [get_ports {c0_ddr4_dqs_t[3]}]
+set_property PACKAGE_PIN E16 [get_ports {c0_ddr4_dqs_c[3]}]
+set_property PACKAGE_PIN A19 [get_ports {c0_ddr4_dqs_t[4]}]
+set_property PACKAGE_PIN A18 [get_ports {c0_ddr4_dqs_c[4]}]
+set_property PACKAGE_PIN N22 [get_ports {c0_ddr4_dqs_t[5]}]
+set_property PACKAGE_PIN M22 [get_ports {c0_ddr4_dqs_c[5]}]
+set_property PACKAGE_PIN M20 [get_ports {c0_ddr4_dqs_t[6]}]
+set_property PACKAGE_PIN L20 [get_ports {c0_ddr4_dqs_c[6]}]
+set_property PACKAGE_PIN H24 [get_ports {c0_ddr4_dqs_t[7]}]
+set_property PACKAGE_PIN G23 [get_ports {c0_ddr4_dqs_c[7]}]
+
+set_property PACKAGE_PIN C8 [get_ports {c0_ddr4_odt[0]}]
+set_property PACKAGE_PIN N20 [get_ports c0_ddr4_reset_n]
+
+##########
+
+

target/xilinx/scripts/common.tcl

@@ -15,6 +15,11 @@ set fpart(vcu128)   "xcvu37p-fsvh2892-2L-e"
 set hwdev(vcu128)   "xcvu37p_0"
 set cfgmp(vcu128)   "mt25qu02g-spi-x1_x2_x4"
 
+# vcu118 board params
+set bpart(vcu118) "xilinx.com:vcu118:part0:2.4"
+set fpart(vcu118) "xcvu9p-flga2104-2L-e"
+set hwdev(vcu118) "xcvu9p_0"
+
 
 # Initialize an implementation project
 proc init_impl {xilinx_root argc argv} {