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treewide: Various build and documentation fixes #106

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Feb 24, 2024
Merged

treewide: Various build and documentation fixes #106

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87c8d74
make: Various fixes
paulsc96 Feb 23, 2024
0fb1aa4
docs: Address issues documented in #92
paulsc96 Feb 23, 2024
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13 changes: 7 additions & 6 deletions cheshire.mk
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Original file line number Diff line number Diff line change
Expand Up @@ -90,8 +90,8 @@ $(OTPROOT)/.generated: $(CHS_ROOT)/hw/rv_plic.cfg.hjson
AXIRT_NUM_MGRS ?= 8
AXIRT_NUM_SUBS ?= 2
include $(AXIRTROOT)/axirt.mk
$(AXIRTROOT)/.generated: axirt_regs
touch $@
$(AXIRTROOT)/.generated:
flock -x $@ $(MAKE) axirt_regs && touch $@

# AXI VGA
include $(AXI_VGA_ROOT)/axi_vga.mk
Expand Down Expand Up @@ -132,20 +132,21 @@ CHS_BOOTROM_ALL += $(CHS_ROOT)/hw/bootrom/cheshire_bootrom.sv $(CHS_ROOT)/hw/boo
# Simulation #
##############

$(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl: Bender.yml
$(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl: $(CHS_ROOT)/Bender.yml
$(BENDER) script vsim -t sim -t cv64a6_imafdcsclic_sv39 -t test -t cva6 -t rtl --vlog-arg="$(VLOG_ARGS)" > $@
echo 'vlog "$(realpath $(CHS_ROOT))/target/sim/src/elfloader.cpp" -ccflags "-std=c++11"' >> $@

.PRECIOUS: $(CHS_ROOT)/target/sim/models
$(CHS_ROOT)/target/sim/models:
mkdir -p $@

# Download (partially non-free) simulation models from publically available sources;
# by running these targets or targets depending on them, you accept this (see README.md).
$(CHS_ROOT)/target/sim/models/s25fs512s.v: Bender.yml | $(CHS_ROOT)/target/sim/models
$(CHS_ROOT)/target/sim/models/s25fs512s.v: $(CHS_ROOT)/Bender.yml | $(CHS_ROOT)/target/sim/models
wget --no-check-certificate https://freemodelfoundry.com/fmf_vlog_models/flash/s25fs512s.v -O $@
touch $@

$(CHS_ROOT)/target/sim/models/24FC1025.v: Bender.yml | $(CHS_ROOT)/target/sim/models
$(CHS_ROOT)/target/sim/models/24FC1025.v: $(CHS_ROOT)/Bender.yml | $(CHS_ROOT)/target/sim/models
wget https://ww1.microchip.com/downloads/en/DeviceDoc/24xx1025_Verilog_Model.zip -o $@
unzip -p 24xx1025_Verilog_Model.zip 24FC1025.v > $@
rm 24xx1025_Verilog_Model.zip
Expand All @@ -158,7 +159,7 @@ CHS_SIM_ALL += $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl
# FPGA Flow #
#############

$(CHS_ROOT)/target/xilinx/scripts/add_sources.tcl: Bender.yml
$(CHS_ROOT)/target/xilinx/scripts/add_sources.tcl: $(CHS_ROOT)/Bender.yml
$(BENDER) script vivado -t fpga -t cv64a6_imafdcsclic_sv39 -t cva6 > $@

CHS_XILINX_ALL += $(CHS_ROOT)/target/xilinx/scripts/add_sources.tcl
Expand Down
8 changes: 4 additions & 4 deletions docs/tg/xilinx.md
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Expand Up @@ -60,7 +60,7 @@ Baremetal code can be preloaded through JTAG using OpenOCD and GDB or loaded fro
First, connect to UART using a serial communication program like minicom:

```
minicom -cD /dev/ttyUSBX
minicom -c on D /dev/ttyUSBX
```

Make sure that hardware flow control matches your board's setup (usually *off*).
Expand Down Expand Up @@ -105,7 +105,7 @@ Clone the `cheshire` branch of CVA6 SDK and build the firmware (OpenSBI + U-boot

```
git submodule update --init --recursive sw/deps/cva6-sdk
make -C sw/deps/cva6-sdk images
cd sw/deps/cva6-sdk && make images
```

In principle, we can boot Linux through JTAG by loading all images into memory, launching OpenSBI, and instructing U-boot to load the kernel directly from memory. Here, we focus on autonomous boot from SD card.
Expand All @@ -115,10 +115,10 @@ In this case, OpenSBI is loaded by a regular baremetal program called the [Zero-
To create a full Linux disk image from the ZSL, device tree, firmware, and Linux, run:

```
make sw/boot/linux.gpt.bin
make ${CHS_ROOT}/sw/boot/linux.gpt.bin
```

Flash this image to an SD card as you did in the previous section, then insert the SD card and reset into boot mode 1. You should first see the ZSL print on the UART:
where `CHS_ROOT` is the root of the Cheshire repository. Flash this image to an SD card as you did in the previous section, then insert the SD card and reset into boot mode 1. You should first see the ZSL print on the UART:

```
/\___/\ Boot mode: 1
Expand Down
6 changes: 3 additions & 3 deletions sw/sw.mk
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Original file line number Diff line number Diff line change
Expand Up @@ -100,14 +100,14 @@ CHS_SW_GEN_HDRS += $(OTPROOT)/.generated
%.o: %.S $(CHS_SW_GEN_HDRS)
$(CHS_SW_CC) $(CHS_SW_INCLUDES) $(CHS_SW_CCFLAGS) -c $< -o $@

define chs_ld_elf_rule
define chs_sw_ld_elf_rule
.PRECIOUS: %.$(1).elf

%.$(1).elf: $$(CHS_SW_LD_DIR)/$(1).ld %.o $$(CHS_SW_LIBS)
$$(CHS_SW_CC) $$(CHS_SW_INCLUDES) -T$$< $$(CHS_SW_LDFLAGS) -o $$@ $$*.o $$(CHS_SW_LIBS)
endef

$(foreach link,$(patsubst $(CHS_SW_LD_DIR)/%.ld,%,$(wildcard $(CHS_SW_LD_DIR)/*.ld)),$(eval $(call chs_ld_elf_rule,$(link))))
$(foreach link,$(patsubst $(CHS_SW_LD_DIR)/%.ld,%,$(wildcard $(CHS_SW_LD_DIR)/*.ld)),$(eval $(call chs_sw_ld_elf_rule,$(link))))

%.dump: %.elf
$(CHS_SW_OBJDUMP) -d -S $< > $@
Expand All @@ -129,7 +129,7 @@ $(foreach link,$(patsubst $(CHS_SW_LD_DIR)/%.ld,%,$(wildcard $(CHS_SW_LD_DIR)/*.
%.gpt.bin: %.rom.bin
rm -f $@
truncate -s $$(( ($$(stat --printf="%s" $<)/512 + 85)*512 )) $@
sgdisk --clear -g --set-alignment=1 --new=1:37:40 --new=2:42:-9 --typecode=2:$(CHS_SW_ZSL_TGUID) --new=3:-5:-2 $@
sgdisk -Z --clear -g --set-alignment=1 --new=1:37:40 --new=2:42:-9 --typecode=2:$(CHS_SW_ZSL_TGUID) --new=3:-5:-2 $@ &> /dev/null
dd if=$< of=$@ bs=512 seek=42 conv=notrunc

# Create hex file from .gpt image
Expand Down
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