Merge pull request #84 from pulp-platform/balasr/soc-reg-tests-2

Add sw reset tests

Makefile

@@ -7,4 +7,3 @@
 CAR_ROOT ?= $(shell pwd)
 
 include carfield.mk
-

carfield.mk

@@ -5,6 +5,8 @@
 # Luca Valente <[email protected]>
 # Alessandro Ottaviano <[email protected]>
 # Yvan Tortorella <[email protected]>
+# Robert Balas <[email protected]>
+# Manuel Eggimann <[email protected]>
 
 CAR_ROOT ?= $(shell $(BENDER) path carfield)
 CHS_ROOT ?= $(CAR_ROOT)/cheshire
@@ -67,7 +69,7 @@ endif
 ######################
 
 CAR_NONFREE_REMOTE ?= [email protected]:carfield/carfield-nonfree.git
-CAR_NONFREE_COMMIT ?= 3c2bf51894b699a49eb8e69e21ade567e1b28b49
+CAR_NONFREE_COMMIT ?= f09457c9aabc3b150ae36c854961e89b679360aa
 
 ## Clone the non-free verification IP for the Carfield TB
 car-nonfree-init:

hw/carfield.sv

@@ -660,12 +660,12 @@ carfield_rstgen #(
 ) i_carfield_rstgen (
   .clks_i(domain_clk),
   .pwr_on_rst_ni,
-  .sw_rsts_ni(~{car_regs_reg2hw.periph_rst.q,
-                car_regs_reg2hw.safety_island_rst.q,
-                car_regs_reg2hw.security_island_rst.q,
-                car_regs_reg2hw.pulp_cluster_rst.q,
+  .sw_rsts_ni(~{car_regs_reg2hw.l2_rst.q,
                 car_regs_reg2hw.spatz_cluster_rst.q,
-                car_regs_reg2hw.l2_rst.q}),
+                car_regs_reg2hw.pulp_cluster_rst.q,
+                car_regs_reg2hw.security_island_rst.q,
+                car_regs_reg2hw.safety_island_rst.q,
+                car_regs_reg2hw.periph_rst.q}),
   .test_mode_i,
   .rsts_no(rsts_n),
   .pwr_on_rsts_no(pwr_on_rsts_n),

sw/include/car_memory_map.h

@@ -36,6 +36,9 @@ extern void *__base_l2;
 #define CAR_SAFETY_ISLAND_SPM_BASE_ADDR 0x60000000
 #define CAR_SAFETY_ISLAND_SPM_END_ADDR  0x60020000
 
+#define CAR_SAFETY_ISLAND_PERIPHS_BASE_ADDR 0x60200000
+#define CAR_SAFETY_ISLAND_PERIPHS_END_ADDR 0x60300000
+
 // Integer Cluster
 #define CAR_INT_CLUSTER_SPM_BASE_ADDR 0x50000000
 #define CAR_INT_CLUSTER_SPM_END_ADDR  0x50040000
@@ -44,6 +47,9 @@ extern void *__base_l2;
 #define CAR_FP_CLUSTER_SPM_BASE_ADDR 0x51000000
 #define CAR_FP_CLUSTER_SPM_END_ADDR  0x51020000
 
+#define CAR_FP_CLUSTER_PERIPHS_BASE_ADDR 0x51020000
+// #define CAR_FP_CLUSTER_PERIPHS_END_ADDR  unknown
+
 // HyperRAM
 #define CAR_HYPERRAM_BASE_ADDR 0x80400000
 #define CAR_HYPERRAM_END_ADDR  0x80800000

sw/include/car_util.h

@@ -0,0 +1,163 @@
+// Copyright 2023 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Robert Balas <[email protected]>
+// Alessandro Ottaviano <[email protected]>
+
+#ifndef __CAR_UTIL_H
+#define __CAR_UTIL_H
+
+#include "util.h"
+#include "car_memory_map.h"
+#include "regs/soc_ctrl.h"
+#include "io.h"
+
+// for the calculation check safety island top
+#define SAFETY_ISLAND_BOOT_ADDR_RSVAL (CAR_SAFETY_ISLAND_PERIPHS_BASE_ADDR + 0x1080)
+
+enum car_isolation_status { CAR_ISOLATE_DISABLE = 0, CAR_ISOLATE_ENABLE = 1 };
+
+enum car_rst_status { CAR_RST_ASSERT = 1, CAR_RST_RELEASE = 0 };
+
+enum car_clk {
+    CAR_HOST_CLK     = 0,
+    CAR_PERIPH_CLK   = 1,
+    CAR_SAFETY_CLK   = 2,
+    CAR_SECURITY_CLK = 3,
+    CAR_PULP_CLK     = 4,
+    CAR_SPATZ_CLK    = 5,
+    CAR_L2_CLK       = 6,
+};
+
+enum car_rst {
+    CAR_PERIPH_RST   = 0,
+    CAR_SAFETY_RST   = 1,
+    CAR_SECURITY_RST = 2,
+    CAR_PULP_RST     = 3,
+    CAR_SPATZ_RST    = 4,
+    CAR_L2_RST       = 5,
+};
+
+// these do not exist so we set a dummy value
+#define CARFIELD_L2_ISOLATE_REG_OFFSET -1
+#define CARFIELD_L2_ISOLATE_STATUS_REG_OFFSET -1
+
+#define CARFIELD_HOST_CLK_EN_REG_OFFSET -1
+#define CARFIELD_HOST_CLK_SEL_REG_OFFSET -1
+#define CARFIELD_HOST_CLK_DIV_VALUE_REG_OFFSET -1
+
+// generate register offset for reset domains from autogenerated soc_ctrl.h
+#define X(NAME)                                                                \
+    static inline uint32_t car_get_##NAME##_offset(enum car_rst rst)           \
+    {                                                                          \
+        switch (rst) {                                                         \
+        case CAR_PERIPH_RST:                                                   \
+            return CARFIELD_PERIPH_##NAME##_REG_OFFSET;                        \
+        case CAR_SAFETY_RST:                                                   \
+            return CARFIELD_SAFETY_ISLAND_##NAME##_REG_OFFSET;                 \
+        case CAR_SECURITY_RST:                                                 \
+            return CARFIELD_SECURITY_ISLAND_##NAME##_REG_OFFSET;               \
+        case CAR_PULP_RST:                                                     \
+            return CARFIELD_PULP_CLUSTER_##NAME##_REG_OFFSET;                  \
+        case CAR_SPATZ_RST:                                                    \
+            return CARFIELD_SPATZ_CLUSTER_##NAME##_REG_OFFSET;                 \
+        case CAR_L2_RST:                                                       \
+            return CARFIELD_L2_##NAME##_REG_OFFSET;                            \
+        default:                                                               \
+            return -1;                                                         \
+        }                                                                      \
+    }
+
+X(RST);
+X(ISOLATE);
+X(ISOLATE_STATUS);
+#undef X
+
+// generate register offset for clock domains from autogenerated soc_ctrl.h
+#define X(NAME)                                                                \
+    static inline uint32_t car_get_##NAME##_offset(enum car_clk clk)           \
+    {                                                                          \
+        switch (clk) {                                                         \
+        case CAR_HOST_CLK:                                                     \
+            return CARFIELD_HOST_##NAME##_REG_OFFSET;                          \
+        case CAR_PERIPH_CLK:                                                   \
+            return CARFIELD_PERIPH_##NAME##_REG_OFFSET;                        \
+        case CAR_SAFETY_CLK:                                                   \
+            return CARFIELD_SAFETY_ISLAND_##NAME##_REG_OFFSET;                 \
+        case CAR_SECURITY_CLK:                                                 \
+            return CARFIELD_SECURITY_ISLAND_##NAME##_REG_OFFSET;               \
+        case CAR_SPATZ_CLK:                                                    \
+            return CARFIELD_SPATZ_CLUSTER_##NAME##_REG_OFFSET;                 \
+        case CAR_L2_CLK:                                                       \
+            return CARFIELD_L2_##NAME##_REG_OFFSET;                            \
+        default:                                                               \
+            return -1;                                                         \
+        }                                                                      \
+    }
+
+X(CLK_EN);
+X(CLK_SEL);
+X(CLK_DIV_VALUE);
+#undef X
+
+static inline enum car_clk car_clkd_from_rstd(enum car_rst rst)
+{
+    switch (rst) {
+    case CAR_PERIPH_RST:
+        return CAR_PERIPH_CLK;
+    case CAR_SAFETY_RST:
+        return CAR_SAFETY_CLK;
+    case CAR_SECURITY_RST:
+        return CAR_SECURITY_CLK;
+    case CAR_PULP_RST:
+        return CAR_PULP_CLK;
+    case CAR_SPATZ_RST:
+        return CAR_SPATZ_CLK;
+    case CAR_L2_RST:
+        return CAR_L2_CLK;
+    }
+}
+
+void car_set_isolate(enum car_rst rst, enum car_isolation_status status)
+{
+    writew(status, CAR_SOC_CTRL_BASE_ADDR + car_get_ISOLATE_offset(rst));
+    fence();
+    while (readw(CAR_SOC_CTRL_BASE_ADDR + car_get_ISOLATE_STATUS_offset(rst)) !=
+           status)
+        ;
+}
+
+void car_enable_clk(enum car_clk clk)
+{
+    writew(1, CAR_SOC_CTRL_BASE_ADDR + car_get_CLK_EN_offset(clk));
+    fence();
+}
+
+void car_disable_clk(enum car_clk clk)
+{
+    writew(0, CAR_SOC_CTRL_BASE_ADDR + car_get_CLK_EN_offset(clk));
+    fence();
+}
+
+void car_set_rst(enum car_rst rst, enum car_rst_status status)
+{
+    writew(status, CAR_SOC_CTRL_BASE_ADDR + car_get_RST_offset(rst));
+    fence();
+}
+
+void car_reset_domain(enum car_rst rst)
+{
+    car_set_isolate(rst, CAR_ISOLATE_ENABLE);
+    car_disable_clk(car_clkd_from_rstd(rst));
+
+    car_set_rst(rst, CAR_RST_ASSERT);
+    for (volatile int i = 0; i < 16; i++)
+        ;
+    car_set_rst(rst, CAR_RST_RELEASE);
+
+    car_enable_clk(car_clkd_from_rstd(rst));
+    car_set_isolate(rst, CAR_ISOLATE_DISABLE);
+}
+
+#endif

sw/include/regs/safety_soc_ctrl.h

@@ -0,0 +1,40 @@
+// Generated register defines for safety_soc_ctrl
+
+// Copyright information found in source file:
+// Copyright 2023 ETH Zurich and University of Bologna
+
+// Licensing information found in source file:
+// 
+// SPDX-License-Identifier: SHL-0.51
+
+#ifndef _SAFETY_SOC_CTRL_REG_DEFS_
+#define _SAFETY_SOC_CTRL_REG_DEFS_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+// Register width
+#define SAFETY_SOC_CTRL_PARAM_REG_WIDTH 32
+
+// Core Boot Address
+#define SAFETY_SOC_CTRL_BOOTADDR_REG_OFFSET 0x0
+
+// Core Fetch Enable
+#define SAFETY_SOC_CTRL_FETCHEN_REG_OFFSET 0x4
+#define SAFETY_SOC_CTRL_FETCHEN_FETCHEN_BIT 0
+
+// Core Return Status (return value, EOC)
+#define SAFETY_SOC_CTRL_CORESTATUS_REG_OFFSET 0x8
+
+// Core Boot Mode
+#define SAFETY_SOC_CTRL_BOOTMODE_REG_OFFSET 0xc
+#define SAFETY_SOC_CTRL_BOOTMODE_BOOTMODE_MASK 0x3
+#define SAFETY_SOC_CTRL_BOOTMODE_BOOTMODE_OFFSET 0
+#define SAFETY_SOC_CTRL_BOOTMODE_BOOTMODE_FIELD \
+  ((bitfield_field32_t) { .mask = SAFETY_SOC_CTRL_BOOTMODE_BOOTMODE_MASK, .index = SAFETY_SOC_CTRL_BOOTMODE_BOOTMODE_OFFSET })
+
+#ifdef __cplusplus
+}  // extern "C"
+#endif
+#endif  // _SAFETY_SOC_CTRL_REG_DEFS_
+// End generated register defines for safety_soc_ctrl