fpga: Removed sim and vcu128

sw/boot/zsl.c

@@ -60,7 +60,7 @@ int main(void) {
     void *priv = (void *)(uintptr_t)*reg32(&__base_regs, CHESHIRE_SCRATCH_1_REG_OFFSET);
 
     // Initialize UART
-    uart_init(&__base_uart, core_freq, __BAUDRATE);
+    uart_init(&__base_uart, core_freq, 115200);
 
     // Print boot-critical cat, and also parameters
     printf(" /\\___/\\       Boot mode:       %d\r\n"

sw/include/params.h

@@ -30,9 +30,6 @@ extern void *__base_axirtgrd;
 extern void *__base_spm;
 extern void *__base_dram;
 
-// ZSL baudrate (may be overriden on slower SoCs)
-static const uint32_t __BAUDRATE = 115200;
-
 // Maximum number of LBAs to copy to SPM for boot (48 KiB)
 static const uint64_t __BOOT_SPM_MAX_LBAS = 2 * 48;
 

sw/lib/hal/uart_debug.c

@@ -24,7 +24,7 @@ int uart_debug_init(void *uart_base, uint64_t core_freq) {
     CHECK_ASSERT(0x11, uart_base != 0);
     CHECK_ASSERT(0x12, core_freq != 0);
     // The UART debug mode uses the sane default 115.2kBaud
-    uart_init(uart_base, core_freq, __BAUDRATE);
+    uart_init(uart_base, core_freq, 115200);
     fence();
     // Nothing went wrong
     return 0;

sw/tests/helloworld.c

@@ -17,7 +17,7 @@ int main(void) {
     char str[] = "Hello World!\r\n";
     uint32_t rtc_freq = *reg32(&__base_regs, CHESHIRE_RTC_FREQ_REG_OFFSET);
     uint64_t reset_freq = clint_get_core_freq(rtc_freq, 2500);
-    uart_init(&__base_uart, reset_freq, __BAUDRATE);
+    uart_init(&__base_uart, reset_freq, 115200);
     uart_write_str(&__base_uart, str, sizeof(str));
     uart_write_flush(&__base_uart);
     return 0;

target/xilinx/flavor_vanilla/flavor_vanilla.mk

@@ -9,7 +9,6 @@
 #
 
 # This flavor requires pre-compiled Xilinx IPs (which may depend on the board)
-chs_xilinx_ips_names_vanilla_vcu128    := xlnx_mig_ddr4 xlnx_clk_wiz xlnx_vio
 chs_xilinx_ips_names_vanilla_genesys2  := xlnx_clk_wiz xlnx_vio xlnx_mig_7_ddr3
 chs_xilinx_ips_names_vanilla           := $(chs_xilinx_ips_names_vanilla_${chs_xilinx_board})
 # Path to compiled ips
@@ -24,19 +23,13 @@ chs_xilinx_ips_paths_vanilla           := $(foreach ip-name,$(chs_xilinx_ips_nam
 chs_xilinx_targs_vanilla := $(chs_xilinx_targs_common) $(foreach ip-name,$(chs_xilinx_ips_names_vanilla),$(addprefix -t ,$(ip-name)))
 chs_xilinx_targs_vanilla += -t flavor_vanilla
 
-# Vivado variables
+# Env used to build the vanilla bitsteasm
 chs_vivado_env_vanilla := \
-    chs_xilinx_board=$(chs_xilinx_board) \
-    xilinx_part=$(xilinx_part) \
-    xilinx_board_long=$(xilinx_board_long) \
-    XILINX_PORT=$(XILINX_PORT) \
-    XILINX_HOST=$(XILINX_HOST) \
-    XILINX_FPGA_PATH=$(XILINX_FPGA_PATH) \
-    xilinx_bit=$(xilinx_bit) \
-    xilinx_ip_paths="$(chs_xilinx_ips_paths_vanilla)" \
+    $(chs_vivado_env_common) \
     ROUTED_DCP=$(ROUTED_DCP) \
     XILINX_CHECK_TIMING=$(XILINX_CHECK_TIMING) \
-    XILINX_ELABORATION_ONLY=$(XILINX_ELABORATION_ONLY)
+    XILINX_ELABORATION_ONLY=$(XILINX_ELABORATION_ONLY) \
+    xilinx_ip_paths="$(chs_xilinx_ips_paths_vanilla)"
 
 #
 # Rules
@@ -48,16 +41,10 @@ $(CHS_XIL_DIR)/flavor_vanilla/scripts/add_sources_%.tcl: Bender.yml
 .PRECIOUS: $(CHS_XIL_DIR)/flavor_vanilla/scripts/add_sources_%.tcl
 
 # Compile bitstream
-$(CHS_XIL_DIR)/flavor_vanilla/out/cheshire_vanilla_%.bit: $(CHS_XIL_DIR)/flavor_vanilla/scripts/add_sources_%.tcl $(chs_xilinx_ips_paths_vanilla)
-	@mkdir -p $(CHS_XIL_DIR)/flavor_vanilla/out $(CHS_XIL_DIR)/flavor_vanilla/builds/cheshire_vanilla_$*
+$(CHS_XIL_DIR)/flavor_vanilla/builds/cheshire_vanilla_genesys2/cheshire_vanilla_genesys2.runs/impl_1/cheshire_top_xilinx.bit: $(CHS_XIL_DIR)/flavor_vanilla/scripts/add_sources_genesys2.tcl $(chs_xilinx_ips_paths_vanilla)
+	@mkdir -p $(CHS_XIL_DIR)/flavor_vanilla/builds/cheshire_vanilla_$*
 	cd $(CHS_XIL_DIR)/flavor_vanilla/builds/cheshire_vanilla_$* && $(chs_vivado_env_vanilla) $(VIVADO) $(VIVADO_FLAGS) -source $(CHS_XIL_DIR)/flavor_vanilla/scripts/run.tcl
-	find $(CHS_XIL_DIR)/flavor_vanilla -name "*.ltx" -o -name "*.bit" -o -name "*routed.rpt" | xargs -I {} cp {} $(CHS_XIL_DIR)/flavor_vanilla/out
-
 
 .PHONY: chs-xil-clean-vanilla
 chs-xil-clean-vanilla:
 	cd $(CHS_XIL_DIR)/flavor_vanilla && rm -rf scripts/add_sources* *.log *.jou builds .Xil/
-
-# Add simulation rules to verify Xilinx IP integration
-
-include $(CHS_XIL_DIR)/flavor_vanilla/sim/sim.mk

target/xilinx/flavor_vanilla/scripts/run.tcl

@@ -6,7 +6,7 @@
 # Nils Wistoff <[email protected]>
 # Cyril Koenig <[email protected]>
 
-set project cheshire_vanilla_$::env(chs_xilinx_board)
+set project cheshire_vanilla_$::env(xilinx_board)
 
 create_project $project . -force -part $::env(xilinx_part)
 set_property board_part $::env(xilinx_board_long) [current_project]
@@ -18,18 +18,18 @@ set_param general.maxThreads 8
 read_ip $::env(xilinx_ip_paths)
 
 # Contraints files selection
-switch $::env(chs_xilinx_board) {
-  "genesys2" - "vcu128" {
+switch $::env(xilinx_board) {
+  "genesys2" {
     import_files -fileset constrs_1 -norecurse ../../constraints/cheshire.xdc
-    import_files -fileset constrs_1 -norecurse ../../constraints/$::env(chs_xilinx_board).xdc
+    import_files -fileset constrs_1 -norecurse ../../constraints/$::env(xilinx_board).xdc
   }
   default {
-    puts "Unknown board $::env(chs_xilinx_board)"
+    puts "Unknown board $::env(xilinx_board)"
     exit 1
   }
 }
 
-source ../../scripts/add_sources_$::env(chs_xilinx_board).tcl
+source ../../scripts/add_sources_$::env(xilinx_board).tcl
 
 set_property top ${project}_top_xilinx [current_fileset]
 
@@ -100,7 +100,7 @@ if ($DEBUG) {
         set netNameLast $netName
     }
     # Need to save save constraints before implementing the core
-    # set_property target_constrs_file cheshire.srcs/constrs_1/imports/constraints/$::env(chs_xilinx_board).xdc [current_fileset -constrset]
+    # set_property target_constrs_file cheshire.srcs/constrs_1/imports/constraints/$::env(xilinx_board).xdc [current_fileset -constrset]
     save_constraints -force
     implement_debug_core
     write_debug_probes -force probes.ltx