LLC Partitioning:

1. Add elaboration parameter `LlcRemapHash` in `cheshire_cfg_t` to switch the hash function used for llc partitioning. 2. Add a simple test in `hello.c` to configure `tagger` and `axi_llc` for partitioning.
pulp-platform · Sep 27, 2023 · ad40bac · ad40bac
1 parent 166b035
commit ad40bac
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Showing 5 changed files with 45 additions and 22 deletions.
diff --git a/Bender.lock b/Bender.lock
@@ -24,7 +24,7 @@ packages:
     - common_verification
     - tech_cells_generic
   axi_llc:
-    revision: 0fd5b5cf26a5899da3ebef02379ea5d48cd43f15
+    revision: 39ee9575279b3d1fe119616be07f485eb33df52b
     version: null
     source:
       Git: https://github.com/pulp-platform/axi_llc.git

diff --git a/Bender.yml b/Bender.yml
@@ -14,7 +14,7 @@ package:
 dependencies:
   apb_uart:                 { git: "https://github.com/pulp-platform/apb_uart.git",               version: 0.2.1  }
   axi:                      { git: "https://github.com/pulp-platform/axi",                        rev: 4fb5a02    }
-  axi_llc:                  { git: "https://github.com/pulp-platform/axi_llc",                    rev: 0fd5b5c    }
+  axi_llc:                  { git: "https://github.com/pulp-platform/axi_llc",                    rev: 39ee957    }
   axi_riscv_atomics:        { git: "https://github.com/pulp-platform/axi_riscv_atomics.git",      version: 0.8.1  }
   axi_rt:                   { git: "https://github.com/pulp-platform/axi_rt.git",                 rev: 6c00b92    }
   axi_vga:                  { git: "https://github.com/pulp-platform/axi_vga.git",                version: 0.1.1  }

diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv
@@ -141,6 +141,7 @@ package cheshire_pkg;
     shrt_bt LlcNumBlocks;
     bit     LlcCachePartition;
     shrt_bt LlcMaxPartition;
+    axi_llc_pkg::algorithm_e LlcRemapHash;
     dw_bt   LlcMaxReadTxns;
     dw_bt   LlcMaxWriteTxns;
     aw_bt   LlcAmoNumCuts;
@@ -494,11 +495,11 @@ package cheshire_pkg;
     // Interconnect
     AddrWidth         : 48,
     AxiDataWidth      : 64,
-    AxiUserWidth      : 8,  // Convention: bit 0 for core(s), bit 1 for serial link TODO: add more bits for llc
+    AxiUserWidth      : 7,  // Convention: bit 0 for core(s), bit 1 for serial link, bit 2-6 for llc & tagger
     AxiMstIdWidth     : 2,
     AxiMaxMstTrans    : 8,
     AxiMaxSlvTrans    : 8,
-    AxiUserAmoMsb     : 6,  // Convention: bit 0 for core(s), bit 1 for serial link
+    AxiUserAmoMsb     : 1,  // Convention: bit 0 for core(s), bit 1 for serial link
     AxiUserAmoLsb     : 0,  // Convention: bit 0 for core(s), bit 1 for serial link
     AxiUserDefault    : 0,
     RegMaxReadTxns    : 8,
@@ -534,6 +535,7 @@ package cheshire_pkg;
     LlcNumBlocks      : 8,
     LlcCachePartition : 1,
     LlcMaxPartition   : 16,
+    LlcRemapHash      : axi_llc_pkg::Modulo,
     LlcMaxReadTxns    : 8,
     LlcMaxWriteTxns   : 8,
     LlcAmoNumCuts     : 1,

diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv
@@ -550,24 +550,25 @@ module cheshire_soc import cheshire_pkg::*; #(
     end
 
     axi_llc_reg_wrap #(
-      .SetAssociativity ( Cfg.LlcSetAssoc  ),
-      .NumLines         ( Cfg.LlcNumLines  ),
-      .NumBlocks        ( Cfg.LlcNumBlocks ),
-      .CachePartition   ( Cfg.LlcCachePartition   ),
-      .MaxPartition     ( Cfg.LlcMaxPartition ),
-      .AxiIdWidth       ( AxiSlvIdWidth    ),
-      .AxiAddrWidth     ( Cfg.AddrWidth    ),
-      .AxiDataWidth     ( Cfg.AxiDataWidth ),
-      .AxiUserWidth     ( Cfg.AxiUserWidth ),
-      .AxiUserIdMsb     ( Cfg.LlcUserAmoMsb ),
-      .AxiUserIdLsb     ( Cfg.LlcUserAmoLsb ),
-      .slv_req_t        ( axi_slv_req_t ),
-      .slv_resp_t       ( axi_slv_rsp_t ),
-      .mst_req_t        ( axi_ext_llc_req_t ),
-      .mst_resp_t       ( axi_ext_llc_rsp_t ),
-      .reg_req_t        ( reg_req_t ),
-      .reg_resp_t       ( reg_rsp_t ),
-      .rule_full_t      ( addr_rule_t )
+      .SetAssociativity ( Cfg.LlcSetAssoc        ),
+      .NumLines         ( Cfg.LlcNumLines        ),
+      .NumBlocks        ( Cfg.LlcNumBlocks       ),
+      .CachePartition   ( Cfg.LlcCachePartition  ),
+      .MaxPartition     ( Cfg.LlcMaxPartition    ),
+      .RemapHash        ( Cfg.LlcRemapHash       ),
+      .AxiIdWidth       ( AxiSlvIdWidth          ),
+      .AxiAddrWidth     ( Cfg.AddrWidth          ),
+      .AxiDataWidth     ( Cfg.AxiDataWidth       ),
+      .AxiUserWidth     ( Cfg.AxiUserWidth       ),
+      .AxiUserIdMsb     ( Cfg.LlcUserAmoMsb      ),
+      .AxiUserIdLsb     ( Cfg.LlcUserAmoLsb      ),
+      .slv_req_t        ( axi_slv_req_t          ),
+      .slv_resp_t       ( axi_slv_rsp_t          ),
+      .mst_req_t        ( axi_ext_llc_req_t      ),
+      .mst_resp_t       ( axi_ext_llc_rsp_t      ),
+      .reg_req_t        ( reg_req_t              ),
+      .reg_resp_t       ( reg_rsp_t              ),
+      .rule_full_t      ( addr_rule_t            )
     ) i_llc (
       .clk_i,
       .rst_ni,

diff --git a/sw/tests/helloworld.c b/sw/tests/helloworld.c
@@ -12,8 +12,28 @@
 #include "dif/uart.h"
 #include "params.h"
 #include "util.h"
+#include "regs/axi_llc.h"
 
 int main(void) {
+
+    // Configure LLC partitioning
+    uint32_t *a = (0x03001054);
+    *a = 0xa000;        // give pat0 size 0xa0
+    a = (0x03001064);   // commit changes for llc
+    *a = 1;
+
+    // Configure
+    a = (0x0300a044);   // set user signal to 1
+    *a = 1;
+    a = (0x0300a000);   // commit changes for tagger
+    *a = 1;
+
+    // Switch LLC into non-SPM mode
+    a = (0x03001000);
+    *a = 0;
+    a = (0x03001010);
+    *a = 1;
+
     char str[] = "Hello World!\r\n";
     uint32_t rtc_freq = *reg32(&__base_regs, CHESHIRE_RTC_FREQ_REG_OFFSET);
     uint64_t reset_freq = clint_get_core_freq(rtc_freq, 2500);