restore req sw

pulp-platform · Oct 29, 2024 · 912c9a9 · 912c9a9
1 parent 2ebc5c6
commit 912c9a9
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Showing 4 changed files with 51 additions and 37 deletions.
diff --git a/Bender.lock b/Bender.lock
@@ -15,8 +15,8 @@ packages:
     - apb
     - register_interface
   axi:
-    revision: 587355b77b8ce94dcd600efbd5d5bd118ff913a7
-    version: 0.39.4
+    revision: 853ede23b2a9837951b74dbdc6d18c3eef5bac7d
+    version: 0.39.5
     source:
       Git: https://github.com/pulp-platform/axi.git
     dependencies:
@@ -44,8 +44,8 @@ packages:
     - common_cells
     - common_verification
   axi_rt:
-    revision: d5f857e74d0a5db4e4a2cc3652ca4f40f29a1484
-    version: 0.0.0-alpha.8
+    revision: 641ea950e24722af747033f2ab85f0e48ea8d7f8
+    version: 0.0.0-alpha.9
     source:
       Git: https://github.com/pulp-platform/axi_rt.git
     dependencies:
@@ -162,7 +162,7 @@ packages:
     - register_interface
     - tech_cells_generic
   pulp-ethernet:
-    revision: 85739c2d1ccd6c1c2ea1c5b95effcace234baa81
+    revision: 97ad4987ce2bc3846413fc90c0ac293ef1d66bf8
     version: null
     source:
       Git: https://github.com/pulp-platform/pulp-ethernet.git

diff --git a/Bender.yml b/Bender.yml
@@ -30,7 +30,7 @@ dependencies:
   riscv-dbg:                { git: "https://github.com/pulp-platform/riscv-dbg.git",              version: 0.8.1  }
   serial_link:              { git: "https://github.com/pulp-platform/serial_link.git",            version: 1.1.1  }
   unbent:                   { git: "https://github.com/pulp-platform/unbent.git",                 version: 0.1.6  }
-  pulp-ethernet:            { git: "https://github.com/pulp-platform/pulp-ethernet.git",          rev: "85739c2"  } # branch: chs-hs
+  pulp-ethernet:            { git: "https://github.com/pulp-platform/pulp-ethernet.git",          rev: "97ad498"  } # branch: chs-hs
 
 export_include_dirs:
   - hw/include
@@ -57,4 +57,4 @@ sources:
       - target/xilinx/src/phy_definitions.svh
       - target/xilinx/src/dram_wrapper_xilinx.sv
       - target/xilinx/src/fan_ctrl.sv
-      - target/xilinx/src/cheshire_top_xilinx.sv
+      - target/xilinx/src/cheshire_top_xilinx.sv
diff --git a/sw/tests/ethernet.c b/sw/tests/ethernet.c
@@ -83,6 +83,9 @@ int main(void) {
   while(!(*reg32(ETH_BASE, IDMA_REQ_READY_OFFSET)));
   // Validate Request to DMA
   *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x1;
+  *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x0;
+  // DMA completes data moving
+  while (!(*reg32(ETH_BASE, IDMA_RSP_VALID_OFFSET)));
 
   // configure ethernet
   *reg32(ETH_BASE, MACLO_OFFSET)          = 0x89000123;
@@ -96,19 +99,24 @@ int main(void) {
   *reg32(ETH_BASE, IDMA_DST_ADDR_OFFSET)  = RX_BASE;
   *reg32(ETH_BASE, IDMA_SRC_PROTO_OFFSET) = 0x5;
   *reg32(ETH_BASE, IDMA_DST_PROTO_OFFSET) = 0x0;
-  *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x1;
 
   while(!(*reg32(ETH_BASE, IDMA_REQ_READY_OFFSET)));
+  *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x1;
+  *reg32(ETH_BASE, IDMA_REQ_VALID_OFFSET) = 0x0;
+
   // wait until DMA moves all data
   while (!(*reg32(ETH_BASE, IDMA_RSP_VALID_OFFSET)));
 
-  uint32_t error = 0;
+  volatile uint32_t error = 0;
 
   for (int i = 0; i < DATA_CHUNK; ++i) {
     volatile uint64_t *rx_addr = (volatile uint64_t*)(RX_BASE + i * sizeof(uint64_t));
-    uint64_t data_read = *rx_addr;
+    volatile uint64_t data_read = *rx_addr;
 
-    if (data_read != data_to_write[i]) error ++;
+    if (data_read != data_to_write[i]) {
+      printf("Error at index %d: expected 0x%lx, got 0x%lx\n", i, data_to_write[i], data_read);
+      error++;
+    }
   }
 
   return error;

diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv
@@ -612,7 +612,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
   import idma_pkg::*;
   localparam REG_BUS_AW          = 32;
   localparam REG_BUS_DW          = 32;
-  
+
   typedef reg_test::reg_driver #(
     .AW(REG_BUS_AW),
     .DW(REG_BUS_DW),
@@ -626,24 +626,24 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
   ) reg_bus_rx (
     .clk_i(clk)
   );
-  
+
   logic reg_error, eth_rx_irq;
   logic dma_en;
   logic [REG_BUS_DW-1:0] rx_rsp_valid;
 
   reg_bus_drv_t reg_drv_rx  = new(reg_bus_rx);
-  
+
   reg_req_t reg_bus_rx_req;
   reg_rsp_t reg_bus_rx_rsp;
 
   `REG_BUS_ASSIGN_TO_REQ (reg_bus_rx_req, reg_bus_rx)
   `REG_BUS_ASSIGN_FROM_RSP (reg_bus_rx, reg_bus_rx_rsp)
- 
+
   axi_mst_req_t axi_req_mem;
   axi_mst_rsp_t axi_rsp_mem;
- 
+
   eth_idma_wrap#(
-    .DataWidth           ( DutCfg.AxiDataWidth  ),    
+    .DataWidth           ( DutCfg.AxiDataWidth  ),
     .AddrWidth           ( DutCfg.AddrWidth     ),
     .UserWidth           ( DutCfg.AxiUserWidth  ),
     .AxiIdWidth          ( DutCfg.AxiMstIdWidth ),
@@ -659,7 +659,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
     .reg_rsp_t           ( reg_rsp_t            )
   ) i_rx_eth_idma_wrap (
     .clk_i               ( clk             ),
-    .rst_ni              ( rst_n           ),  
+    .rst_ni              ( rst_n           ),
     .eth_clk125_i        ( eth_clk125      ),
     .eth_clk125q_i       ( eth_clk125q     ),
     .phy_rx_clk_i        ( eth_txck        ),
@@ -668,7 +668,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
     .phy_tx_clk_o        ( eth_rxck        ),
     .phy_txd_o           ( eth_rxd         ),
     .phy_tx_ctl_o        ( eth_rxctl       ),
-    .phy_resetn_o        ( eth_rstn        ),  
+    .phy_resetn_o        ( eth_rstn        ),
     .phy_intn_i          ( 1'b1            ),
     .phy_pme_i           ( 1'b1            ),
     .phy_mdio_i          ( 1'b0            ),
@@ -701,7 +701,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
     .axi_req_i          ( axi_req_mem       ),
     .axi_rsp_o          ( axi_rsp_mem       )
   );
-  
+
   initial begin
     forever begin
     eth_clk125 <= 1;
@@ -723,7 +723,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
   end
 
   initial begin
-    
+
     wait_for_reset();
 
     @(posedge clk)
@@ -733,7 +733,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
 
     reg_drv_rx.send_write( 'h0300c004, 32'h00800207, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0
     @(posedge clk);
-    
+
     @(posedge eth_rx_irq);
 
     while(1) begin
@@ -742,10 +742,10 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
         break;
       @(posedge clk);
     end
-    
-    reg_drv_rx.send_write( 'h0300c01c, 32'h0, 'hf, reg_error ); // SRC_ADDR  
+
+    reg_drv_rx.send_write( 'h0300c01c, 32'h0, 'hf, reg_error ); // SRC_ADDR
     @(posedge clk);
-    
+
     reg_drv_rx.send_write( 'h0300c020, 32'h0, 'hf, reg_error); // DST_ADDR
     @(posedge clk);
 
@@ -757,7 +757,10 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
 
     reg_drv_rx.send_write( 'h0300c044, 'h1, 'hf , reg_error);   // req valid
     @(posedge clk);
-
+
+    reg_drv_rx.send_write( 'h0300c044, 'h0, 'hf , reg_error);   // req valid
+    @(posedge clk);
+
     //wait till all data written into rx_axi_sim_mem
     while(1) begin
       reg_drv_rx.send_read( 'h0300c050, rx_rsp_valid, reg_error);
@@ -770,29 +773,32 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
     // Tx test starts here: external back to core
     reg_drv_rx.send_write( 'h0300c000, 32'h89000123, 'hf, reg_error); //lower 32bits of MAC address
     @(posedge clk);
-  
+
     reg_drv_rx.send_write( 'h0300c004, 32'h00800207, 'hf, reg_error); //upper 16bits of MAC address + other configuration set to false/0
     @(posedge clk);
 
-    reg_drv_rx.send_write( 'h0300c01c, 32'h0, 'hf, reg_error ); // SRC_ADDR  
+    reg_drv_rx.send_write( 'h0300c01c, 32'h0, 'hf, reg_error ); // SRC_ADDR
     @(posedge clk);
-  
+
     reg_drv_rx.send_write( 'h0300c020, 32'h0, 'hf, reg_error); // DST_ADDR
     @(posedge clk);
 
-    reg_drv_rx.send_write( 'h0300c024, 32'h40,'hf , reg_error); // Size in bytes 
+    reg_drv_rx.send_write( 'h0300c024, 32'h40,'hf , reg_error); // Size in bytes
     @(posedge clk);
-  
+
     reg_drv_rx.send_write( 'h0300c028, 32'h0,'hf , reg_error); // src protocol
     @(posedge clk);
 
     reg_drv_rx.send_write( 'h0300c02c, 32'h5,'hf , reg_error); // dst protocol
     @(posedge clk);
 
     reg_drv_rx.send_write( 'h0300c044, 'h1, 'hf , reg_error);   // req valid
-    @(posedge clk);    
-  end 
-
+    @(posedge clk);
+
+    reg_drv_rx.send_write( 'h0300c044, 'h0, 'hf , reg_error);   // req valid
+    @(posedge clk);
+  end
+
   ///////////////////
   //  Serial Link  //
   ///////////////////
@@ -1134,7 +1140,7 @@ module vip_cheshire_soc_tristate import cheshire_pkg::*; (
   // Ethernet pad IO
   input  logic                  eth_mdio_o,
   output logic                  eth_mdio_i,
-  input  logic                  eth_mdio_en,     
+  input  logic                  eth_mdio_en,
   // I2C wires
   inout  wire i2c_sda,
   inout  wire i2c_scl,
@@ -1170,7 +1176,7 @@ module vip_cheshire_soc_tristate import cheshire_pkg::*; (
   end
 
   // Ethernet
-  bufif1 (eth_mdio_i, eth_mdio, ~eth_mdio_en); 
-  bufif1 (eth_mdio, eth_mdio_o, eth_mdio_en);  
+  bufif1 (eth_mdio_i, eth_mdio, ~eth_mdio_en);
+  bufif1 (eth_mdio, eth_mdio_o, eth_mdio_en);
 
 endmodule