cva6: Bump pulp-v1

Signed-off-by: Nils Wistoff <[email protected]>
pulp-platform · Jan 30, 2024 · 81a0bf3 · 81a0bf3
1 parent ca073d1
commit 81a0bf3
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Showing 2 changed files with 58 additions and 23 deletions.
diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv
@@ -463,15 +463,55 @@ package cheshire_pkg;
     endcase
   endfunction
 
-  function automatic ariane_pkg::ariane_cfg_t gen_cva6_cfg(cheshire_cfg_t cfg);
+  function automatic config_pkg::cva6_cfg_t gen_cva6_cfg(cheshire_cfg_t cfg);
     doub_bt SizeSpm = get_llc_size(cfg);
     doub_bt SizeLlcOut = cfg.LlcOutRegionEnd - cfg.LlcOutRegionStart;
     doub_bt CieBase   = cfg.Cva6ExtCieOnTop ? 64'h8000_0000 - cfg.Cva6ExtCieLength : 64'h2000_0000;
     doub_bt NoCieBase = cfg.Cva6ExtCieOnTop ? 64'h2000_0000 : 64'h2000_0000 + cfg.Cva6ExtCieLength;
-    return ariane_pkg::ariane_cfg_t'{
+    return config_pkg::cva6_cfg_t'{
+      NrCommitPorts         : 2,
+      AxiAddrWidth          : cfg.AddrWidth,
+      AxiDataWidth          : cfg.AxiDataWidth,
+      AxiIdWidth            : Cva6IdWidth,
+      AxiUserWidth          : cfg.AxiUserWidth,
+      NrLoadBufEntries      : 2,
+      FpuEn                 : 1,
+      XF16                  : 0,
+      XF16ALT               : 0,
+      XF8                   : 0,
+      XF8ALT                : 1,
+      RVA                   : 1,
+      RVV                   : 0,
+      RVC                   : 1,
+      RVH                   : 1,
+      RVZCB                 : 1,
+      XFVec                 : 0,
+      CvxifEn               : 0,
+      ZiCondExtEn           : 1,
+      RVSCLIC               : 1,
+      RVF                   : 1,
+      RVD                   : 1,
+      FpPresent             : 1,
+      NSX                   : 0,
+      FLen                  : 64,
+      RVFVec                : 0,
+      XF16Vec               : 0,
+      XF16ALTVec            : 0,
+      XF8Vec                : 0,
+      NrRgprPorts           : 0,
+      NrWbPorts             : 0,
+      EnableAccelerator     : 0,
+      RVS                   : 1,
+      RVU                   : 1,
+      HaltAddress           : AmDbg + 'h800,
+      ExceptionAddress      : AmDbg + 'h808,
       RASDepth              : cfg.Cva6RASDepth,
       BTBEntries            : cfg.Cva6BTBEntries,
       BHTEntries            : cfg.Cva6BHTEntries,
+      DmBaseAddress         : AmDbg,
+      NrPMPEntries          : cfg.Cva6NrPMPEntries,
+      NOCType               : config_pkg::NOC_TYPE_AXI4_ATOP,
+      CLICNumInterruptSrc   : NumCoreIrqs + NumIntIntrs + cfg.NumExtClicIntrs,
       NrNonIdempotentRules  : 2,   // Periphs, ExtNonCIE
       NonIdempotentAddrBase : {64'h0000_0000, NoCieBase},
       NonIdempotentLength   : {64'h1000_0000, 64'h6000_0000 - cfg.Cva6ExtCieLength},
@@ -481,12 +521,10 @@ package cheshire_pkg;
       NrCachedRegionRules   : 3,   // CachedSPM, LLCOut, ExtCIE
       CachedRegionAddrBase  : {AmSpm,   cfg.LlcOutRegionStart,  CieBase},
       CachedRegionLength    : {SizeSpm, SizeLlcOut,             cfg.Cva6ExtCieLength},
-      AxiCompliant          : 1,
-      SwapEndianess         : 0,
-      CLICNumInterruptSrc   : NumCoreIrqs + NumIntIntrs + cfg.NumExtClicIntrs,
-      CLICIntCtlBits        : cfg.ClicIntCtlBits,
-      DmBaseAddress         : AmDbg,
-      NrPMPEntries          : cfg.Cva6NrPMPEntries
+      MaxOutstandingStores  : 7,
+      DebugEn               : 1,
+      NonIdemPotenceEn      : 0,
+      AxiBurstWriteEn       : 0
     };
   endfunction
 
@@ -501,9 +539,9 @@ package cheshire_pkg;
 
   localparam cheshire_cfg_t DefaultCfg = '{
     // CVA6 parameters
-    Cva6RASDepth      : ariane_pkg::ArianeDefaultConfig.RASDepth,
-    Cva6BTBEntries    : ariane_pkg::ArianeDefaultConfig.BTBEntries,
-    Cva6BHTEntries    : ariane_pkg::ArianeDefaultConfig.BHTEntries,
+    Cva6RASDepth      : 2,
+    Cva6BTBEntries    : 32,
+    Cva6BHTEntries    : 128,
     Cva6NrPMPEntries  : 0,
     Cva6ExtCieLength  : 'h2000_0000,  // [0x2.., 0x4..) is CIE, [0x4.., 0x8..) is non-CIE
     Cva6ExtCieOnTop   : 0,
@@ -517,7 +555,7 @@ package cheshire_pkg;
     NumExtClicIntrs   : NumExtPlicIntrs,
     NumExtOutIntrTgts : 0,
     NumExtOutIntrs    : 0,
-    ClicIntCtlBits    : ariane_pkg::ArianeDefaultConfig.CLICIntCtlBits,
+    ClicIntCtlBits    : 256,
     NumExtIntrSyncs   : 2,
     // Interconnect
     AddrWidth         : 48,

diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv
@@ -548,7 +548,7 @@ module cheshire_soc import cheshire_pkg::*; #(
 
   `CHESHIRE_TYPEDEF_AXI_CT(axi_cva6, addr_t, cva6_id_t, axi_data_t, axi_strb_t, axi_user_t)
 
-  localparam ariane_pkg::ariane_cfg_t Cva6Cfg = gen_cva6_cfg(Cfg);
+  localparam config_pkg::cva6_cfg_t Cva6Cfg = gen_cva6_cfg(Cfg);
 
   // Boot from boot ROM only if available, otherwise from platform ROM
   localparam logic [63:0] BootAddr = 64'(Cfg.Bootrom ? AmBrom : Cfg.PlatformRom);
@@ -591,15 +591,14 @@ module cheshire_soc import cheshire_pkg::*; #(
 
     // Currently, we support only one core
     cva6 #(
-      .ArianeCfg      ( Cva6Cfg ),
-      .AxiAddrWidth   ( Cfg.AddrWidth ),
-      .AxiDataWidth   ( Cfg.AxiDataWidth ),
-      .AxiIdWidth     ( Cva6IdWidth ),
+      .CVA6Cfg        ( Cva6Cfg ),
       .axi_ar_chan_t  ( axi_cva6_ar_chan_t ),
       .axi_aw_chan_t  ( axi_cva6_aw_chan_t ),
       .axi_w_chan_t   ( axi_cva6_w_chan_t  ),
-      .axi_req_t      ( axi_cva6_req_t ),
-      .axi_rsp_t      ( axi_cva6_rsp_t )
+      .b_chan_t       ( axi_cva6_b_chan_t  ),
+      .r_chan_t       ( axi_cva6_r_chan_t  ),
+      .noc_req_t      ( axi_cva6_req_t ),
+      .noc_resp_t     ( axi_cva6_rsp_t )
     ) i_core_cva6 (
       .clk_i,
       .rst_ni,
@@ -620,10 +619,8 @@ module cheshire_soc import cheshire_pkg::*; #(
       .rvfi_o           ( ),
       .cvxif_req_o      ( ),
       .cvxif_resp_i     ( '0 ),
-      .l15_req_o        ( ),
-      .l15_rtrn_i       ( '0 ),
-      .axi_req_o        ( core_out_req ),
-      .axi_resp_i       ( core_out_rsp )
+      .noc_req_o        ( core_out_req ),
+      .noc_resp_i       ( core_out_rsp )
     );
 
     if (Cfg.BusErr) begin : gen_cva6_bus_err