UNBENT: Allow for custom Err bits on AXI user

pulp-platform · Sep 21, 2023 · 7eb6554 · 7eb6554
1 parent f7568e2
commit 7eb6554
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Showing 4 changed files with 13 additions and 9 deletions.
diff --git a/Bender.lock b/Bender.lock
@@ -170,8 +170,8 @@ packages:
     dependencies:
     - common_verification
   unbent:
-    revision: 791420b326c6455595b4444c02f05f180b99dd06
-    version: 0.1.1
+    revision: 89ea12018002e6fae51f88e25320e79f57db8073
+    version: 0.1.5
     source:
       Git: https://github.com/pulp-platform/unbent.git
     dependencies:

diff --git a/Bender.yml b/Bender.yml
@@ -28,7 +28,7 @@ dependencies:
   serial_link:              { git: "https://github.com/pulp-platform/serial_link.git",            version: 1.1.0  }
   clic:                     { git: "https://github.com/pulp-platform/clic.git",                   version: 2.0.0  }
   irq_router:               { git: "https://github.com/pulp-platform/irq_router.git",             rev: d1d3135    }  # TODO: master commit; use next release once out
-  unbent:                   { git: "https://github.com/pulp-platform/unbent.git",                 version: 0.1.1  }
+  unbent:                   { git: "https://github.com/pulp-platform/unbent.git",                 version: 0.1.5  }
 
 export_include_dirs:
   - hw/include

diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv
@@ -97,6 +97,8 @@ package cheshire_pkg;
     // A '0 user signal indicates no atomics.
     dw_bt   AxiUserAmoMsb;
     dw_bt   AxiUserAmoLsb;
+    dw_bt   AxiUserErrBits;
+    dw_bt   AxiUserErrLsb;
     doub_bt AxiUserDefault; // Default user assignment, adjusted by user features (AMO)
     // Reg parameters
     dw_bt   RegMaxReadTxns;
@@ -523,6 +525,8 @@ package cheshire_pkg;
     AxiMaxSlvTrans    : 24,
     AxiUserAmoMsb     : 1, // Convention: lower AMO bits for cores, MSB for serial link
     AxiUserAmoLsb     : 0, // Convention: lower AMO bits for cores, MSB for serial link
+    AxiUserErrBits    : 0,
+    AxiUserErrLsb     : 0,
     AxiUserDefault    : 0,
     RegMaxReadTxns    : 8,
     RegMaxWriteTxns   : 8,

diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv
@@ -634,8 +634,8 @@ module cheshire_soc import cheshire_pkg::*; #(
       axi_err_unit_wrap #(
         .AddrWidth          ( Cfg.AddrWidth ),
         .IdWidth            ( Cva6IdWidth   ),
-        .UserErrBits        ( 0 ),
-        .UserErrBitsOffset  ( 0 ),
+        .UserErrBits        ( Cfg.AxiUserErrBits ),
+        .UserErrBitsOffset  ( Cfg.AxiUserErrLsb ),
         .NumOutstanding     ( Cfg.CoreMaxTxns ),
         .NumStoredErrors    ( 4 ),
         .DropOldest         ( 1'b0 ),
@@ -1488,8 +1488,8 @@ module cheshire_soc import cheshire_pkg::*; #(
       axi_err_unit_wrap #(
         .AddrWidth          ( Cfg.AddrWidth     ),
         .IdWidth            ( Cfg.AxiMstIdWidth ),
-        .UserErrBits        ( 0 ),
-        .UserErrBitsOffset  ( 0 ),
+        .UserErrBits        ( Cfg.AxiUserErrBits ),
+        .UserErrBitsOffset  ( Cfg.AxiUserErrLsb ),
         .NumOutstanding     ( Cfg.CoreMaxTxns ),
         .NumStoredErrors    ( 4 ),
         .DropOldest         ( 1'b0 ),
@@ -1660,8 +1660,8 @@ module cheshire_soc import cheshire_pkg::*; #(
       axi_err_unit_wrap #(
         .AddrWidth          ( Cfg.AddrWidth     ),
         .IdWidth            ( Cfg.AxiMstIdWidth ),
-        .UserErrBits        ( 0 ),
-        .UserErrBitsOffset  ( 0 ),
+        .UserErrBits        ( Cfg.AxiUserErrBits ),
+        .UserErrBitsOffset  ( Cfg.AxiUserErrLsb ),
         .NumOutstanding     ( Cfg.CoreMaxTxns ),
         .NumStoredErrors    ( 4 ),
         .DropOldest         ( 1'b0 ),