Dual CVA6 in permanent lockstep succesfully works.

pulp-platform · Nov 30, 2023 · 79e44ec · 79e44ec
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commit 79e44ec
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diff --git a/Bender.lock b/Bender.lock
@@ -24,7 +24,7 @@ packages:
     - common_verification
     - tech_cells_generic
   axi_llc:
-    revision: 7d7fc1349d4915a657de535a491bc26fbf0d2cfa
+    revision: 76933aa7fa8ff5c8ccbc075f6af4fca4d8416d17
     version: null
     source:
       Git: https://github.com/pulp-platform/axi_llc
@@ -92,7 +92,7 @@ packages:
       Git: https://github.com/pulp-platform/common_verification.git
     dependencies: []
   cva6:
-    revision: 33557d22d4383bda7251fe5d5e854af6510349b7
+    revision: 70d285ba5b0486b8393dd417e3a7febf80c231fc
     version: null
     source:
       Git: https://github.com/pulp-platform/cva6.git

diff --git a/Bender.yml b/Bender.yml
@@ -14,15 +14,15 @@ package:
 dependencies:
   apb_uart:                 { git: "https://github.com/pulp-platform/apb_uart.git",               version: 0.2.1  }
   axi:                      { git: "https://github.com/pulp-platform/axi",                        rev: 4fb5a02    }
-  axi_llc:                  { git: "https://github.com/pulp-platform/axi_llc",                    rev: 7d7fc13    }
+  axi_llc:                  { git: "https://github.com/pulp-platform/axi_llc",                    rev: 76933aa    } # branch: astral
   axi_riscv_atomics:        { git: "https://github.com/pulp-platform/axi_riscv_atomics.git",      version: 0.8.1  }
   axi_rt:                   { git: "https://github.com/pulp-platform/axi_rt.git",                 version: 0.0.0-alpha.4 }
   axi_vga:                  { git: "https://github.com/pulp-platform/axi_vga.git",                version: 0.1.1  }
   clic:                     { git: "https://github.com/pulp-platform/clic.git",                   rev: "94e2a77"  } # branch: aottaviano/dev
   clint:                    { git: "https://github.com/pulp-platform/clint.git",                  version: 0.2.0  }
   common_cells:             { git: "https://github.com/pulp-platform/common_cells.git",           version: 1.32.0 }
   common_verification:      { git: "https://github.com/pulp-platform/common_verification.git",    version: 0.2.0  }
-  cva6:                     { git: "https://github.com/pulp-platform/cva6.git",                   rev: "33557d2"  } # branch: astral
+  cva6:                     { git: "https://github.com/pulp-platform/cva6.git",                   rev: "70d285b"  } # branch: astral
   iDMA:                     { git: "https://github.com/pulp-platform/iDMA.git",                   version: 0.5.1  }
   irq_router:               { git: "https://github.com/pulp-platform/irq_router.git",             version: 0.0.1-beta.1 }
   opentitan_peripherals:    { git: "https://github.com/pulp-platform/opentitan_peripherals.git",  version: 0.4.0  }

diff --git a/hw/bootrom/cheshire_bootrom.sv b/hw/bootrom/cheshire_bootrom.sv
diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv
@@ -141,6 +141,7 @@ package cheshire_pkg;
     bit     IrqRouter;
     bit     BusErr;
     bit     Cva6DMR;
+    bit     RapidRecovery;
     // Parameters for Debug Module
     jtag_idcode_t DbgIdCode;
     dw_bt   DbgMaxReqs;
@@ -572,6 +573,7 @@ package cheshire_pkg;
     IrqRouter         : 0,
     BusErr            : 1,
     Cva6DMR           : 1,
+    RapidRecovery     : 0,
     // Debug
     DbgIdCode         : CheshireIdCode,
     DbgMaxReqs        : 4,

diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv
@@ -590,8 +590,8 @@ module cheshire_soc import cheshire_pkg::*; #(
   axi_mst_req_t [AxiIn.num_in-1:0] tagger_req;
   axi_mst_rsp_t [AxiIn.num_in-1:0] tagger_rsp;
 
-  axi_cva6_req_t [NumIntHarts-1:0] core_out_req , core_ur_req;
-  axi_cva6_rsp_t [NumIntHarts-1:0] core_out_rsp , core_ur_rsp;
+  axi_cva6_req_t [NumIntHarts-1:0] core_out_req, core_ur_req;
+  axi_cva6_rsp_t [NumIntHarts-1:0] core_out_rsp, core_ur_rsp;
 
   // CLIC interface
   logic [NumIntHarts-1:0] clic_irq_valid, clic_irq_ready;
@@ -603,8 +603,6 @@ module cheshire_soc import cheshire_pkg::*; #(
   logic [NumIntHarts-1:0] [5:0]        clic_irq_vsid;
   riscv::priv_lvl_t  [NumIntHarts] clic_irq_priv;
 
-  // Currently, we support only one core
-  // Actually we should support 2?
   cva6_wrap #(
     .Cva6Cfg          ( Cva6Cfg              ),
     .NumHarts         ( NumIntHarts          ),

diff --git a/hw/cva6_wrap.sv b/hw/cva6_wrap.sv
@@ -139,16 +139,16 @@ for (genvar i = 0; i < NumHarts; i++) begin: gen_cva6_cores
 end
 
 hmr_unit #(
-  .NumCores          ( NumHarts       ),
-  .DMRSupported      ( Cfg.Cva6DMR    ),
-  .DMRFixed          ( 0              ), // TODO: make configurable
-  .TMRSupported      ( 0              ),
-  .RapidRecovery     ( 1              ),
-  .SeparateData      ( 0              ),
-  .RfAddrWidth       ( 5              ),
-  .SysDataWidth      ( 64             ),
-  .all_inputs_t      ( cva6_inputs_t  ), // Inputs from the system to the HMR
-  .nominal_outputs_t ( cva6_outputs_t ),
+  .NumCores          ( NumHarts          ),
+  .DMRSupported      ( Cfg.Cva6DMR       ),
+  .DMRFixed          ( 1                 ), // TODO: make configurable
+  .TMRSupported      ( 0                 ),
+  .RapidRecovery     ( Cfg.RapidRecovery ),
+  .SeparateData      ( 0                 ),
+  .RfAddrWidth       ( 5                 ),
+  .SysDataWidth      ( 64                ),
+  .all_inputs_t      ( cva6_inputs_t     ), // Inputs from the system to the HMR
+  .nominal_outputs_t ( cva6_outputs_t    ),
   // .core_backup_t     ( '0 ), // TODO
   // .bus_outputs_t     ( '0 ), // TODO
   .reg_req_t         ( reg_req_t ), // TODO
@@ -176,8 +176,8 @@ hmr_unit #(
   .rapid_recovery_o ( /* TODO */ ),
   .core_backup_i    (  '0        ), // TODO
 
-  .sys_inputs_i          ( sys2hmr ),
-  .sys_nominal_outputs_o ( hmr2sys ),
+  .sys_inputs_i          ( sys2hmr[0] ),
+  .sys_nominal_outputs_o ( hmr2sys[0] ),
   .sys_bus_outputs_o     (         ),
   .sys_fetch_en_i        ( '0      ), // TODO?
   .enable_bus_vote_i     ( '0      ), // TODO?
@@ -188,4 +188,7 @@ hmr_unit #(
   .core_bus_outputs_i     ( '0           ) // TODO?
 );
 
+/* We temporarily hardcode this for permanent lockstep.*/
+assign hmr2sys[NumHarts-1] = '0;
+
 endmodule: cva6_wrap
diff --git a/sw/include/smp.h b/sw/include/smp.h
@@ -17,12 +17,16 @@
     csrr reg2, mhartid; \
     bne reg1, reg2, 2f
 
+// If the two cores are lockestepped at reset or peremanetly locked, we see a
+// single Hart ID at boot. Otherwise we see more than one.
 #define smp_resume(reg1, reg2, reg3) \
     la reg1, __base_clint; \
     la reg3, __base_regs; \
     lw reg3, 76(reg3); /* regs.NUM_INT_HARTS */ \
-    slli reg3, reg3, 2; \
-    add reg3, reg1, reg3; \
+    csrr reg2, mhartid; /* If the non-SMP hart is lockstepped, it will not execute this. */ \
+    addi reg2, reg2, 1; /* Compute the shift-amount for the CLINT depending on the Hart ID. */ \
+    sll reg3, reg3, reg2; \
+    add reg3, reg1, reg3; /* Result CLINT register we want to set or reset. */ \
     1:; \
     li reg2, 1; \
     sw reg2, 0(reg1); \