target/xilinx: Clean up flow, multi-board support, add VCU128

.gitignore

@@ -35,3 +35,8 @@ target/sim/vsim/modelsim.ini
 target/sim/vsim/transcript
 target/sim/vsim/vsim.wlf
 target/sim/vsim/work/
+
+# Xilinx generated files
+target/xilinx/build
+target/xilinx/out
+target/xilinx/scripts/add_sources.*

Bender.yml

@@ -53,5 +53,7 @@ sources:
 
   - target: all(fpga, xilinx)
     files:
+      - target/xilinx/src/phy_definitions.svh
+      - target/xilinx/src/dram_wrapper_xilinx.sv
       - target/xilinx/src/fan_ctrl.sv
       - target/xilinx/src/cheshire_top_xilinx.sv

cheshire.mk

@@ -158,18 +158,15 @@ CHS_SIM_ALL += $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl
 # FPGA Flow #
 #############
 
-$(CHS_ROOT)/target/xilinx/scripts/add_sources.tcl: Bender.yml
-	$(BENDER) script vivado -t fpga -t cv64a6_imafdcsclic_sv39 -t cva6 > $@
-
-CHS_XILINX_ALL += $(CHS_ROOT)/target/xilinx/scripts/add_sources.tcl
+include target/xilinx/xilinx.mk
 
 #################################
 # Phonies (KEEP AT END OF FILE) #
 #################################
 
 .PHONY: chs-all chs-nonfree-init chs-clean-deps chs-sw-all chs-hw-all chs-bootrom-all chs-sim-all chs-xilinx-all
 
-CHS_ALL += $(CHS_SW_ALL) $(CHS_HW_ALL) $(CHS_SIM_ALL) $(CHS_XILINX_ALL)
+CHS_ALL += $(CHS_SW_ALL) $(CHS_HW_ALL) $(CHS_SIM_ALL)
 
 chs-all:         $(CHS_ALL)
 chs-sw-all:      $(CHS_SW_ALL)

target/xilinx/constraints/cheshire.xdc

@@ -4,67 +4,38 @@
 #
 # Nicole Narr <[email protected]>
 # Christopher Reinwardt <[email protected]>
+# Cyril Koenig <[email protected]>
+# Paul Scheffler <[email protected]>
 
-###################
-# Global Settings #
-###################
+#################
+# Clock routing #
+#################
 
-# Testmode is set to 0 during normal use
-set_case_analysis 0 [get_ports test_mode_i]
+# JTAG is on non-clock-capable GPIOs (if not using BSCANE)
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_ports jtag_tck_i]]
+set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_ports jtag_tck_i]]
 
-# Preserve the output mux of the clock divider
-set_property DONT_TOUCH TRUE [get_cells i_sys_clk_div/i_clk_bypass_mux]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_ports   sys_reset*]]
+set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_ports sys_reset*]]
 
-# The pin of which we get the 200 MHz single ended clock from the MIG
-set MIG_CLK_SRC {i_dram/ui_clk}
+# Remove avoid tc_clk_mux2 to use global clock routing
+set all_in_mux [get_nets -of [ get_pins -filter { DIRECTION == IN } -of [get_cells -hier -filter { ORIG_REF_NAME == tc_clk_mux2 || REF_NAME == tc_clk_mux2 }]]]
+set_property CLOCK_DEDICATED_ROUTE FALSE $all_in_mux
+set_property CLOCK_BUFFER_TYPE NONE $all_in_mux
 
-#####################
-# Timing Parameters #
-#####################
-
-# 200 MHz FPGA diff clock
-set FPGA_TCK 5.0
-
-# 50 MHz SoC clock
-set SOC_TCK 20.0
+########
+# JTAG #
+########
 
-# 10 MHz JTAG clock
+# 10 MHz (max) JTAG clock
 set JTAG_TCK 100.0
 
-# I2C High-speed mode is 3.2 Mb/s
-set I2C_IO_SPEED 312.5
-
-# UART speed is at most 5 Mb/s
-set UART_IO_SPEED 200.0
-
-##########
-# Clocks #
-##########
-
-# System Clock
-create_generated_clock -name clk_soc -source [get_pins $MIG_CLK_SRC] -divide_by 4 [get_pins i_sys_clk_div/i_clk_bypass_mux/i_BUFGMUX/O]
-
 # JTAG Clock
 create_clock -period $JTAG_TCK -name clk_jtag [get_ports jtag_tck_i]
 set_input_jitter clk_jtag 1.000
 
-################
-# Clock Groups #
-################
-
 # JTAG Clock is asynchronous to all other clocks
-set_clock_groups -name jtag_async -asynchronous -group [get_clocks clk_jtag]
-
-#######################
-# Placement Overrides #
-#######################
-
-# Accept suboptimal BUFG-BUFG cascades
-set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_sys_clk_div/i_clk_mux/clk0_i]
-
-########
-# JTAG #
-########
+set_clock_groups -name jtag_async -asynchronous -group {clk_jtag}
 
 set_input_delay  -min -clock clk_jtag [expr 0.10 * $JTAG_TCK] [get_ports {jtag_tdi_i jtag_tms_i}]
 set_input_delay  -max -clock clk_jtag [expr 0.20 * $JTAG_TCK] [get_ports {jtag_tdi_i jtag_tms_i}]
@@ -75,79 +46,26 @@ set_output_delay -max -clock clk_jtag [expr 0.20 * $JTAG_TCK] [get_ports jtag_td
 set_max_delay  -from [get_ports jtag_trst_ni] $JTAG_TCK
 set_false_path -hold -from [get_ports jtag_trst_ni]
 
-#######
-# MIG #
-#######
-
-set_max_delay  -from [get_pins i_dram/u_xlnx_mig_7_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C] $FPGA_TCK
-set_false_path -hold -from [get_pins i_dram/u_xlnx_mig_7_ddr3_mig/u_ddr3_infrastructure/rstdiv0_sync_r1_reg_rep/C]
-
-########
-# SPIM #
-########
-
-set_input_delay  -min -clock clk_soc [expr 0.10 * $SOC_TCK] [get_ports {sd_d_* sd_cd_i}]
-set_input_delay  -max -clock clk_soc [expr 0.35 * $SOC_TCK] [get_ports {sd_d_* sd_cd_i}]
-set_output_delay -min -clock clk_soc [expr 0.10 * $SOC_TCK] [get_ports {sd_d_* sd_*_o}]
-set_output_delay -max -clock clk_soc [expr 0.20 * $SOC_TCK] [get_ports {sd_d_* sd_*_o}]
-
-#######
-# I2C #
-#######
-
-set_max_delay [expr $I2C_IO_SPEED * 0.35] -from [get_ports {i2c_scl_io i2c_sda_io}]
-set_false_path -hold -from [get_ports {i2c_scl_io i2c_sda_io}]
-
-set_max_delay [expr $I2C_IO_SPEED * 0.35] -to [get_ports {i2c_scl_io i2c_sda_io}]
-set_false_path -hold -to [get_ports {i2c_scl_io i2c_sda_io}]
-
 ########
 # UART #
 ########
 
+# UART speed is at most 5 Mb/s
+set UART_IO_SPEED 200.0
+
 set_max_delay [expr $UART_IO_SPEED * 0.35] -from [get_ports uart_rx_i]
 set_false_path -hold -from [get_ports uart_rx_i]
 
 set_max_delay [expr $UART_IO_SPEED * 0.35] -to [get_ports uart_tx_o]
 set_false_path -hold -to [get_ports uart_tx_o]
 
-#######
-# VGA #
-#######
-
-set_output_delay -min -clock clk_soc [expr $SOC_TCK * 0.10] [get_ports vga*]
-set_output_delay -max -clock clk_soc [expr $SOC_TCK * 0.35] [get_ports vga*]
-
-############
-# Switches #
-############
-
-set_input_delay -min -clock clk_soc [expr $SOC_TCK * 0.10] [get_ports {boot_mode* fan_sw* test_mode_i}]
-set_input_delay -max -clock clk_soc [expr $SOC_TCK * 0.35] [get_ports {boot_mode* fan_sw* test_mode_i}]
-
-set_output_delay -min -clock clk_soc [expr $SOC_TCK * 0.10] [get_ports fan_pwm]
-set_output_delay -max -clock clk_soc [expr $SOC_TCK * 0.35] [get_ports fan_pwm]
-
-set_max_delay [expr 2 * $SOC_TCK] -from [get_ports {boot_mode* fan_sw* test_mode_i}]
-set_false_path -hold -from [get_ports {boot_mode* fan_sw* test_mode_i}]
-
-set_max_delay [expr 2 * $SOC_TCK] -to [get_ports fan_pwm]
-set_false_path -hold -to [get_ports fan_pwm]
-
 ########
 # CDCs #
 ########
 
-# cdc_fifo_gray: Disable hold checks, limit datapath delay and bus skew
-set_property KEEP_HIERARCHY SOFT [get_cells i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*i_sync]
-set_false_path -hold -through [get_pins -of_objects [get_cells i_axi_cdc_mig/i_axi_cdc_*]] -through [get_pins -of_objects [get_cells i_axi_cdc_mig/i_axi_cdc_*]]
-set_max_delay -datapath -from [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_dst_*/*i_sync/reg*/D] $FPGA_TCK
-set_max_delay -datapath -from [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_src_*/*i_sync/reg*/D] $FPGA_TCK
-set_max_delay -datapath -from [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] $FPGA_TCK
-
-###################
-# Reset Generator #
-###################
+# Disable hold checks on CDCs
+set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {ORIG_REF_NAME=="sync" || REF_NAME=="sync"}]
+set_false_path -hold -through [get_pins -of_objects [get_cells -hier -filter {ORIG_REF_NAME=="sync" || REF_NAME=="sync"}] -filter {NAME=~*serial_i}]
 
-set_max_delay -from [get_pins {i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C}] $SOC_TCK
-set_false_path -hold -from [get_pins {i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C}]
+set_false_path -hold -through [get_pins -of_objects [get_cells -hier -filter {ORIG_REF_NAME == axi_cdc_src || REF_NAME == axi_cdc_src}] -filter {NAME =~ *async*}]
+set_false_path -hold -through [get_pins -of_objects [get_cells -hier -filter {ORIG_REF_NAME == axi_cdc_dst || REF_NAME == axi_cdc_dst}] -filter {NAME =~ *async*}]