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LLC Partition: Add LLC partitioning part into cheshire.
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Update the axi-test for llc partitioning tests.

WIP: Ensure correct FPGA behavior (CI test)
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@DiyouS @alex96295
DiyouS authored and alex96295 committed Sep 27, 2023
1 parent 498ef70 commit 64fee40
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Showing 9 changed files with 195 additions and 21 deletions.
15 changes: 13 additions & 2 deletions Bender.lock
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Expand Up @@ -24,8 +24,8 @@ packages:
- common_verification
- tech_cells_generic
axi_llc:
revision: 559bcbd09a5a884dbe31e2d72fd95d024e357f39
version: 0.2.1
revision: 39ee9575279b3d1fe119616be07f485eb33df52b
version: null
source:
Git: https://github.com/pulp-platform/axi_llc.git
dependencies:
Expand Down Expand Up @@ -171,6 +171,17 @@ packages:
- axi
- common_cells
- register_interface
tagger:
revision: 044d92c17728e7c608cd6678d01ec2d749c7ab83
version: null
source:
Git: [email protected]:dishen/tagger.git
dependencies:
- axi
- common_cells
- common_verification
- register_interface
- tech_cells_generic
tech_cells_generic:
revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf
version: 0.2.13
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5 changes: 3 additions & 2 deletions Bender.yml
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Expand Up @@ -13,8 +13,8 @@ package:

dependencies:
apb_uart: { git: "https://github.com/pulp-platform/apb_uart.git", version: 0.2.1 }
axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.0 }
axi_llc: { git: "https://github.com/pulp-platform/axi_llc.git", version: 0.2.1 }
axi: { git: "https://github.com/pulp-platform/axi", rev: 4fb5a02 }
axi_llc: { git: "https://github.com/pulp-platform/axi_llc", rev: 39ee957 }
axi_riscv_atomics: { git: "https://github.com/pulp-platform/axi_riscv_atomics.git", version: 0.8.1 }
axi_rt: { git: "https://github.com/pulp-platform/axi_rt.git", version: 0.0.0-alpha.3 }
axi_vga: { git: "https://github.com/pulp-platform/axi_vga.git", version: 0.1.1 }
Expand All @@ -29,6 +29,7 @@ dependencies:
register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.2 }
riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.8.0 }
serial_link: { git: "https://github.com/pulp-platform/serial_link.git", version: 1.1.0 }
tagger: { git: "[email protected]:dishen/tagger.git", rev: 044d92c }
unbent: { git: "https://github.com/pulp-platform/unbent.git", version: 0.1.5 }

export_include_dirs:
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17 changes: 17 additions & 0 deletions cheshire.mk
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Expand Up @@ -11,11 +11,16 @@ BENDER ?= bender
VLOG_ARGS ?= -suppress 2583 -suppress 13314
VSIM ?= vsim

MAXPARTITION ?= 16
CACHE_PARTITION ?= 1


# Define used paths (prefixed to avoid name conflicts)
CHS_ROOT ?= $(shell $(BENDER) path cheshire)
CHS_REG_DIR := $(shell $(BENDER) path register_interface)
CHS_SLINK_DIR := $(shell $(BENDER) path serial_link)
CHS_LLC_DIR := $(shell $(BENDER) path axi_llc)
CHS_TAGGER_DIR := $(shell $(BENDER) path tagger)

# Define paths used in dependencies
OTPROOT := $(shell $(BENDER) path opentitan_peripherals)
Expand Down Expand Up @@ -103,12 +108,24 @@ $(CHS_SLINK_DIR)/.generated: $(CHS_ROOT)/hw/serial_link.hjson
cp $< $(dir $@)/src/regs/serial_link_single_channel.hjson
flock -x $@ $(MAKE) -C $(CHS_SLINK_DIR) update-regs && touch $@

# LLC partitioning configuration
$(CHS_LLC_DIR)/.generated:
$(MAKE) -C $(CHS_LLC_DIR) REGWIDTH=64 CACHENUMLINES=256 MAXPARTITION=$(MAXPARTITION) CACHE_PARTITION=$(CACHE_PARTITION) regs
@touch $@

# Tagger configuration
$(CHS_TAGGER_DIR)/.generated:
$(MAKE) -C $(CHS_TAGGER_DIR) REGWIDTH=32 MAXPARTITION=$(MAXPARTITION) PATID_LEN=5 regs
@touch $@

CHS_HW_ALL += $(CHS_ROOT)/hw/regs/cheshire_reg_pkg.sv $(CHS_ROOT)/hw/regs/cheshire_reg_top.sv
CHS_HW_ALL += $(CLINTROOT)/.generated
CHS_HW_ALL += $(OTPROOT)/.generated
CHS_HW_ALL += $(AXIRTROOT)/.generated
CHS_HW_ALL += $(AXI_VGA_ROOT)/.generated
CHS_HW_ALL += $(CHS_SLINK_DIR)/.generated
CHS_HW_ALL += $(CHS_LLC_DIR)/.generated
CHS_HW_ALL += $(CHS_TAGGER_DIR)/.generated

#####################
# Generate Boot ROM #
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1 change: 1 addition & 0 deletions hw/bootrom/cheshire_bootrom.S
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Expand Up @@ -62,6 +62,7 @@ _start:
andi t0, t0, 2 // regs.HW_FEATURES.llc
beqz t0, _prom_check_run
la t0, __base_llc
// Only configure half of LLC as SPM
_wait_llc_bist:
lw t1, 72(t0) // llc.BIST_STATUS_DONE_BIT
beqz t1, _wait_llc_bist
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15 changes: 14 additions & 1 deletion hw/cheshire_pkg.sv
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Expand Up @@ -147,13 +147,18 @@ package cheshire_pkg;
shrt_bt LlcSetAssoc;
shrt_bt LlcNumLines;
shrt_bt LlcNumBlocks;
bit LlcCachePartition;
shrt_bt LlcMaxPartition;
axi_llc_pkg::algorithm_e LlcRemapHash;
dw_bt LlcMaxReadTxns;
dw_bt LlcMaxWriteTxns;
aw_bt LlcAmoNumCuts;
bit LlcAmoPostCut;
bit LlcOutConnect;
doub_bt LlcOutRegionStart;
doub_bt LlcOutRegionEnd;
dw_bt LlcUserAmoMsb;
dw_bt LlcUserAmoLsb;
// Parameters for VGA
byte_bt VgaRedWidth;
byte_bt VgaGreenWidth;
Expand Down Expand Up @@ -384,6 +389,7 @@ package cheshire_pkg;
aw_bt irq_router;
aw_bt [2**MaxCoresWidth-1:0] bus_err;
aw_bt [2**MaxCoresWidth-1:0] clic;
aw_bt tagger;
aw_bt ext_base;
aw_bt num_out;
aw_bt num_rules;
Expand All @@ -404,6 +410,7 @@ package cheshire_pkg;
if (cfg.Gpio) begin i++; ret.gpio = i; r++; ret.map[r] = '{i, 'h0300_5000, 'h0300_6000}; end
if (cfg.SerialLink) begin i++; ret.slink = i; r++; ret.map[r] = '{i, AmSlink, AmSlink +'h1000}; end
if (cfg.Vga) begin i++; ret.vga = i; r++; ret.map[r] = '{i, 'h0300_7000, 'h0300_8000}; end
if (cfg.LlcCachePartition) begin i++; ret.tagger = i; r++; ret.map[r] = '{i, 'h0300_a000, 'h0300_b000}; end
if (cfg.IrqRouter) begin i++; ret.irq_router = i; r++; ret.map[r] = '{i, 'h0208_0000, 'h020c_0000}; end
if (cfg.AxiRt) begin i++; ret.axirt = i; r++; ret.map[r] = '{i, 'h020c_0000, 'h0210_0000}; end
if (cfg.Clic) for (int j = 0; j < cfg.NumCores; j++) begin
Expand Down Expand Up @@ -521,7 +528,7 @@ package cheshire_pkg;
// Interconnect
AddrWidth : 48,
AxiDataWidth : 64,
AxiUserWidth : 2, // AMO(2)
AxiUserWidth : 2, // Convention: bit 0 for core(s), bit 1 for serial link
AxiMstIdWidth : 2,
AxiMaxMstTrans : 24,
AxiMaxSlvTrans : 24,
Expand Down Expand Up @@ -568,6 +575,12 @@ package cheshire_pkg;
LlcOutConnect : 1,
LlcOutRegionStart : 'h8000_0000,
LlcOutRegionEnd : 'h1_0000_0000,
LlcUserAmoMsb : 6,
LlcUserAmoLsb : 2,
// LLC Partitioning
LlcCachePartition : 0,
LlcMaxPartition : 0,
LlcRemapHash : axi_llc_pkg::Modulo,
// VGA: RGB332
VgaRedWidth : 3,
VgaGreenWidth : 3,
Expand Down
71 changes: 55 additions & 16 deletions hw/cheshire_soc.sv
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Expand Up @@ -495,6 +495,7 @@ module cheshire_soc import cheshire_pkg::*; #(
// This is necessary for routing in the LLC-internal interconnect.
always_comb begin
axi_llc_remap_req = axi_llc_cut_req;

if (axi_llc_cut_req.aw.addr & ~AmSpmRegionMask == AmSpmBaseUncached & ~AmSpmRegionMask)
axi_llc_remap_req.aw.addr = AmSpm | (AmSpmRegionMask & axi_llc_cut_req.aw.addr);
if (axi_llc_cut_req.ar.addr & ~AmSpmRegionMask == AmSpmBaseUncached & ~AmSpmRegionMask)
Expand All @@ -503,20 +504,25 @@ module cheshire_soc import cheshire_pkg::*; #(
end

axi_llc_reg_wrap #(
.SetAssociativity ( Cfg.LlcSetAssoc ),
.NumLines ( Cfg.LlcNumLines ),
.NumBlocks ( Cfg.LlcNumBlocks ),
.AxiIdWidth ( AxiSlvIdWidth ),
.AxiAddrWidth ( Cfg.AddrWidth ),
.AxiDataWidth ( Cfg.AxiDataWidth ),
.AxiUserWidth ( Cfg.AxiUserWidth ),
.slv_req_t ( axi_slv_req_t ),
.slv_resp_t ( axi_slv_rsp_t ),
.mst_req_t ( axi_ext_llc_req_t ),
.mst_resp_t ( axi_ext_llc_rsp_t ),
.reg_req_t ( reg_req_t ),
.reg_resp_t ( reg_rsp_t ),
.rule_full_t ( addr_rule_t )
.SetAssociativity ( Cfg.LlcSetAssoc ),
.NumLines ( Cfg.LlcNumLines ),
.NumBlocks ( Cfg.LlcNumBlocks ),
.CachePartition ( Cfg.LlcCachePartition ),
.MaxPartition ( Cfg.LlcMaxPartition ),
.RemapHash ( Cfg.LlcRemapHash ),
.AxiIdWidth ( AxiSlvIdWidth ),
.AxiAddrWidth ( Cfg.AddrWidth ),
.AxiDataWidth ( Cfg.AxiDataWidth ),
.AxiUserWidth ( Cfg.AxiUserWidth ),
.AxiUserIdMsb ( Cfg.LlcUserAmoMsb ),
.AxiUserIdLsb ( Cfg.LlcUserAmoLsb ),
.slv_req_t ( axi_slv_req_t ),
.slv_resp_t ( axi_slv_rsp_t ),
.mst_req_t ( axi_ext_llc_req_t ),
.mst_resp_t ( axi_ext_llc_rsp_t ),
.reg_req_t ( reg_req_t ),
.reg_resp_t ( reg_rsp_t ),
.rule_full_t ( addr_rule_t )
) i_llc (
.clk_i,
.rst_ni,
Expand Down Expand Up @@ -581,6 +587,9 @@ module cheshire_soc import cheshire_pkg::*; #(

assign intr.intn.bus_err.cores = core_bus_err_intr_comb;

axi_mst_req_t tagger_req;
axi_mst_rsp_t tagger_rsp;

for (genvar i = 0; i < NumIntHarts; i++) begin : gen_cva6_cores
axi_cva6_req_t core_out_req, core_ur_req;
axi_cva6_rsp_t core_out_rsp, core_ur_rsp;
Expand Down Expand Up @@ -742,9 +751,39 @@ module cheshire_soc import cheshire_pkg::*; #(
.rst_ni,
.slv_req_i ( core_ur_req ),
.slv_resp_o ( core_ur_rsp ),
.mst_req_o ( axi_in_req[AxiIn.cores[i]] ),
.mst_resp_i ( axi_in_rsp[AxiIn.cores[i]] )
.mst_req_o ( tagger_req ),
.mst_resp_i ( tagger_rsp )
// .mst_req_o ( axi_in_req[AxiIn.cores[i]] ),
// .mst_resp_i ( axi_in_rsp[AxiIn.cores[i]] )
);

if (Cfg.LlcCachePartition) begin : gen_tagger

tagger #(
.DATA_WIDTH ( Cfg.AxiDataWidth ),
.ADDR_WIDTH ( Cfg.AddrWidth ),
.MAXPARTITION ( Cfg.LlcMaxPartition ),
.AXI_USER_ID_MSB ( Cfg.LlcUserAmoMsb ),
.AXI_USER_ID_LSB ( Cfg.LlcUserAmoLsb ),
.TAGGER_GRAN ( 3 ),
.axi_req_t ( axi_mst_req_t ),
.axi_rsp_t ( axi_mst_rsp_t ),
.reg_req_t ( reg_req_t ),
.reg_rsp_t ( reg_rsp_t )
) i_tagger (
.clk_i,
.rst_ni,
.slv_req_i ( tagger_req ),
.slv_rsp_o ( tagger_rsp ),
.mst_req_o ( axi_in_req[AxiIn.cores[i]] ),
.mst_rsp_i ( axi_in_rsp[AxiIn.cores[i]] ),
.cfg_req_i ( reg_out_req[RegOut.tagger] ),
.cfg_rsp_o ( reg_out_rsp[RegOut.tagger] )
);
end else begin

Check warning on line 783 in hw/cheshire_soc.sv

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GitHub Actions / verible-verilog-lint

[verible-verilog-lint] hw/cheshire_soc.sv#L783 

All generate block statements must have a label [Style: generate-statements] [generate-label]
Raw output 
message:"All generate block statements must have a label [Style: generate-statements] [generate-label]"  location:{path:"hw/cheshire_soc.sv"  range:{start:{line:783  column:14}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
assign axi_in_req[AxiIn.cores[i]] = tagger_req;
assign tagger_rsp = axi_in_rsp[AxiIn.cores[i]];
end
end

/////////////////////////
Expand Down
68 changes: 68 additions & 0 deletions sw/include/regs/axi_llc.h
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Expand Up @@ -72,6 +72,74 @@ extern "C" {
#define AXI_LLC_BIST_STATUS_REG_OFFSET 0x48
#define AXI_LLC_BIST_STATUS_DONE_BIT 0

// Index-based Partition Flush Configuration [31:0] (lower 32 bit)
#define AXI_LLC_CFG_FLUSH_PARTITION_LOW_REG_OFFSET 0x4c

// Index-based Partition Flush Configuration [63:32] (upper 32 bit)
#define AXI_LLC_CFG_FLUSH_PARTITION_HIGH_REG_OFFSET 0x50

// Index-based Partition Configuration [31:0] (lower 32 bit) (common
// parameters)
#define AXI_LLC_CFG_SET_PARTITION_LOW_LOW_FIELD_WIDTH 32
#define AXI_LLC_CFG_SET_PARTITION_LOW_LOW_FIELDS_PER_REG 1
#define AXI_LLC_CFG_SET_PARTITION_LOW_MULTIREG_COUNT 2

// Index-based Partition Configuration [31:0] (lower 32 bit)
#define AXI_LLC_CFG_SET_PARTITION_LOW_0_REG_OFFSET 0x54

// Index-based Partition Configuration [31:0] (lower 32 bit)
#define AXI_LLC_CFG_SET_PARTITION_LOW_1_REG_OFFSET 0x58

// Index-based Partition Configuration [63:32] (higher 32 bit) (common
// parameters)
#define AXI_LLC_CFG_SET_PARTITION_HIGH_HIGH_FIELD_WIDTH 32
#define AXI_LLC_CFG_SET_PARTITION_HIGH_HIGH_FIELDS_PER_REG 1
#define AXI_LLC_CFG_SET_PARTITION_HIGH_MULTIREG_COUNT 2

// Index-based Partition Configuration [63:32] (higher 32 bit)
#define AXI_LLC_CFG_SET_PARTITION_HIGH_0_REG_OFFSET 0x5c

// Index-based Partition Configuration [63:32] (higher 32 bit)
#define AXI_LLC_CFG_SET_PARTITION_HIGH_1_REG_OFFSET 0x60

// Commit the set partition configuration
#define AXI_LLC_COMMIT_PARTITION_CFG_REG_OFFSET 0x64
#define AXI_LLC_COMMIT_PARTITION_CFG_COMMIT_BIT 0

// Index-based Flushed Flag (lower 32 bit) (common parameters)
#define AXI_LLC_FLUSHED_SET_LOW_LOW_FIELD_WIDTH 32
#define AXI_LLC_FLUSHED_SET_LOW_LOW_FIELDS_PER_REG 1
#define AXI_LLC_FLUSHED_SET_LOW_MULTIREG_COUNT 4

// Index-based Flushed Flag (lower 32 bit)
#define AXI_LLC_FLUSHED_SET_LOW_0_REG_OFFSET 0x6c

// Index-based Flushed Flag (lower 32 bit)
#define AXI_LLC_FLUSHED_SET_LOW_1_REG_OFFSET 0x70

// Index-based Flushed Flag (lower 32 bit)
#define AXI_LLC_FLUSHED_SET_LOW_2_REG_OFFSET 0x74

// Index-based Flushed Flag (lower 32 bit)
#define AXI_LLC_FLUSHED_SET_LOW_3_REG_OFFSET 0x78

// Index-based Flushed Flag (upper 32 bit) (common parameters)
#define AXI_LLC_FLUSHED_SET_HIGH_HIGH_FIELD_WIDTH 32
#define AXI_LLC_FLUSHED_SET_HIGH_HIGH_FIELDS_PER_REG 1
#define AXI_LLC_FLUSHED_SET_HIGH_MULTIREG_COUNT 4

// Index-based Flushed Flag (upper 32 bit)
#define AXI_LLC_FLUSHED_SET_HIGH_0_REG_OFFSET 0x7c

// Index-based Flushed Flag (upper 32 bit)
#define AXI_LLC_FLUSHED_SET_HIGH_1_REG_OFFSET 0x80

// Index-based Flushed Flag (upper 32 bit)
#define AXI_LLC_FLUSHED_SET_HIGH_2_REG_OFFSET 0x84

// Index-based Flushed Flag (upper 32 bit)
#define AXI_LLC_FLUSHED_SET_HIGH_3_REG_OFFSET 0x88

#ifdef __cplusplus
} // extern "C"
#endif
Expand Down
20 changes: 20 additions & 0 deletions sw/tests/helloworld.c
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Expand Up @@ -12,8 +12,28 @@
#include "dif/uart.h"
#include "params.h"
#include "util.h"
#include "regs/axi_llc.h"

int main(void) {

// Configure LLC partitioning
uint32_t *a = (0x03001054);
*a = 0xa000; // give pat0 size 0xa0
a = (0x03001064); // commit changes for llc
*a = 1;

// Configure
a = (0x0300a044); // set user signal to 1
*a = 1;
a = (0x0300a000); // commit changes for tagger
*a = 1;

// Switch LLC into non-SPM mode
a = (0x03001000);
*a = 0;
a = (0x03001010);
*a = 1;

char str[] = "Hello World!\r\n";
uint32_t rtc_freq = *reg32(&__base_regs, CHESHIRE_RTC_FREQ_REG_OFFSET);
uint64_t reset_freq = clint_get_core_freq(rtc_freq, 2500);
Expand Down
4 changes: 4 additions & 0 deletions target/xilinx/src/cheshire_top_xilinx.sv
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Expand Up @@ -123,6 +123,10 @@ module cheshire_top_xilinx
LlcOutConnect : 1,
LlcOutRegionStart : 'h8000_0000,
LlcOutRegionEnd : 'h1_0000_0000,
// LLC partitioning
LlcCachePartition : 0,
LlcMaxPartition : 0,
LlcRemapHash : axi_llc_pkg::Modulo,
// VGA: RGB332
VgaRedWidth : 5,
VgaGreenWidth : 6,
Expand Down

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