Merge pull request #90 from pulp-platform/yt/offloading

Add PULP Cluster Offloading
pulp-platform · Aug 3, 2023 · 52e5c79 · 52e5c79
2 parents 7d74026 + 6ff3527
commit 52e5c79
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Showing 21 changed files with 316 additions and 129 deletions.
diff --git a/Bender.local b/Bender.local
@@ -6,7 +6,7 @@ overrides:
   axi:                  { git: https://github.com/pulp-platform/axi.git                   , version: 0.39.1-beta }
   apb:                  { git: "https://github.com/pulp-platform/apb.git"                 , version: 0.2.3 }
   register_interface:   { git: "https://github.com/pulp-platform/register_interface.git"  , version: 0.4.1 }
-  redundancy_cells:     { git: "https://github.com/pulp-platform/redundancy_cells.git"    , rev: "6a011b6" } # branch: michaero/hmr-alt
+  redundancy_cells:     { git: "https://github.com/pulp-platform/redundancy_cells.git"    , rev: "482d2f5" } # branch: yt/rapidrecovery
   tech_cells_generic:   { git: "https://github.com/pulp-platform/tech_cells_generic.git"  , version: =0.2.11                                }
   riscv-dbg:            { git: "https://github.com/pulp-platform/riscv-dbg.git"           , version: =0.8.0                                 }
   idma:                 { git: "https://github.com/pulp-platform/idma.git"                , rev:     437ffa9                                }

diff --git a/Bender.lock b/Bender.lock
@@ -243,13 +243,13 @@ packages:
     dependencies:
     - common_cells
   fpu_interco:
-    revision: c985d54c2b078ddfbec8c2a498f453410bbdc93e
+    revision: 4aec4b68424947b0c4cf25fd7c4b907cb9ec3dfa
     version: null
     source:
       Git: https://github.com/pulp-platform/fpu_interco.git
     dependencies:
-    - cv32e40p
     - fpnew
+    - riscv
   hci:
     revision: b2e6f391aa6c10c03f45b693d80a0aaddecf169b
     version: null
@@ -381,7 +381,7 @@ packages:
     dependencies:
     - axi_slice
   pulp_cluster:
-    revision: ebc7d1888e2242ea8cb579aab1113e02e08367b4
+    revision: 201453dbcedc8f7235b2723363356ba5845e5120
     version: null
     source:
       Git: https://github.com/pulp-platform/pulp_cluster.git
@@ -423,7 +423,7 @@ packages:
     - hwpe-stream
     - tech_cells_generic
   redundancy_cells:
-    revision: 6a011b6f5acf3eca202ed847d6c64474a0bc7cb5
+    revision: 482d2f5ed05f25c851f4048f1bd402cc0d2b58b6
     version: null
     source:
       Git: https://github.com/pulp-platform/redundancy_cells.git
@@ -443,7 +443,7 @@ packages:
     - common_cells
     - common_verification
   riscv:
-    revision: 6187537f9994d16bad2d721c0f5ebc5193c0f010
+    revision: dd086242d10f248b4051a1fc67ae2b35b989c29c
     version: null
     source:
       Git: [email protected]:AlSaqr-platform/riscv_nn.git
@@ -497,7 +497,7 @@ packages:
     - common_cells
     - register_interface
   spatz:
-    revision: 1506445bea978dfa81e0d717a005e84e6fa450b5
+    revision: 56544dc2e50acd08cf2c3909267d7daf19f5be19
     version: null
     source:
       Git: [email protected]:spatz/spatz.git

diff --git a/Bender.yml b/Bender.yml
@@ -16,14 +16,14 @@ dependencies:
   hyperbus:           { git: https://github.com/pulp-platform/hyperbus.git,             rev: 2adb7271438cdb96c19fbaf3e2a6bf89ffeee568 } # branch: lv/phys_in_use
   car_l2:             { git: [email protected]:carfield/carfield_l2_mem.git,       rev: d6ab486b2777bf78c38b49352b5977565a272a58 } # branch: main
   safety_island:      { git: [email protected]:carfield/safety-island.git,         rev: b0501345b1741fa96b781ef5d845026fec036fd2 } # branch: param_banks
-  pulp_cluster:       { git: https://github.com/pulp-platform/pulp_cluster.git,         rev: ebc7d1888e2242ea8cb579aab1113e02e08367b4 } # branch: ck/carfield-1
+  pulp_cluster:       { git: https://github.com/pulp-platform/pulp_cluster.git,         rev: 201453dbcedc8f7235b2723363356ba5845e5120 } # branch: yt/rapidrecovery
   opentitan:          { git: https://github.com/alsaqr-platform/opentitan.git,          rev: 245d92fe49dc6be32afe3bfb6a133778002d4880 } # branch: carfield
   mailbox_unit:       { git: [email protected]:pulp-platform/mailbox_unit.git,             version: 1.1.0                                }
   apb:                { git: https://github.com/pulp-platform/apb.git,                  version: 0.2.3                                }
   timer_unit:         { git: https://github.com/pulp-platform/timer_unit.git,           version: 1.0.2                                }
   apb_adv_timer:      { git: https://github.com/pulp-platform/apb_adv_timer.git,        version: 1.0.4                                }
   can_bus:            { git: [email protected]:AlSaqr-platform/can_bus.git,                rev: 230222cc568b49b39a3385b12edaf680657bc69d }
-  spatz:              { git: [email protected]:spatz/spatz.git,                    rev: 1506445bea978dfa81e0d717a005e84e6fa450b5 } # branch: aottaviano/sync-regs
+  spatz:              { git: [email protected]:spatz/spatz.git,                    rev: 56544dc2e50acd08cf2c3909267d7daf19f5be19 } # branch: aottaviano/sync-regs
   bus_err_unit:       { git: [email protected]:carfield/bus_err_unit.git,          rev: 47a6436dc4b4b7f4a44f7786033b22c6d01530b2 } # branch: main
   common_cells:       { git: https://github.com/pulp-platform/common_cells.git,         version: 1.30.0                               }
 

diff --git a/README.md b/README.md
@@ -57,9 +57,20 @@ Follow these steps to launch a Carfield simulation:
 * Compile tests for Carfield. Tests resides in `sw/tests`.
 
   ```
+  // Compile Safety Island standalone software
+  source ./scripts/safed-env.sh
+  make safed-sw-build
+  // Compile Integer cluster standalone software
+  source ./scripts/pulpd-env.sh
+  make pulpd-sw-build
+  // Compile Cheshire SW
   make car-sw-build
   ```
 
+  The latter commands:
+  * Compiles safety island and pulp cluster standalone tests
+  * Compiles CVA6 standalone and offloading tests
+
 ### System bootmodes
 
 * The current supported bootmodes from Cheshire are:
@@ -78,7 +89,7 @@ Follow these steps to launch a Carfield simulation:
   of preload, if any is needed. For RTL simulation, bootmodes 0, 2 and 3 are supported. SPI SD card
   bootmode is supported on FPGA emulation.
 
-* The current supported bootmodes ffrom the Safety Island are:
+* The current supported bootmodes for the Safety Island are:
 
   | `SAFED_BOOTMODE` | Action |
   | --- | --- |

diff --git a/carfield.mk b/carfield.mk
@@ -37,7 +37,7 @@ CHS_ROOT ?= $(shell $(BENDER) path cheshire)
 
 CHS_BOOTMODE ?= 0 # default passive bootmode
 CHS_PRELMODE ?= 1 # default serial link preload
-CHS_BINARY   ?= 
+CHS_BINARY   ?=
 CHS_IMAGE    ?=
 
 # Safety Island
@@ -52,8 +52,8 @@ SECD_BINARY   ?=
 SECD_BOOTMODE ?=
 
 # PULP cluster
-PULPCL_ROOT   ?= $(shell $(BENDER) path pulp_cluster)
-PULPCL_BINARY ?=
+PULPD_ROOT   ?= $(shell $(BENDER) path pulp_cluster)
+PULPD_BINARY ?=
 
 # Spatz cluster
 SPATZCL_ROOT    ?= $(shell $(BENDER) path spatz)
@@ -90,7 +90,7 @@ endif
 ######################
 
 CAR_NONFREE_REMOTE ?= [email protected]:carfield/carfield-nonfree.git
-CAR_NONFREE_COMMIT ?= df886d3eea670dffdbe4d632a64c7b123b9fac76
+CAR_NONFREE_COMMIT ?= a51afe8cd67a47b83df79e1d0f53d5a8cf22371d
 
 ## Clone the non-free verification IP for the Carfield TB
 car-nonfree-init:
@@ -191,7 +191,7 @@ car-hw-sim:
 		 set SECD_BINARY $(SECD_BINARY); \
 		 set SAFED_BOOTMODE $(SAFED_BOOTMODE); \
 		 set SAFED_BINARY $(SAFED_BINARY); \
-		 set PULPCL_BINARY $(PULPCL_BINARY); \
+		 set PULPD_BINARY $(PULPD_BINARY); \
 		 set SPATZCL_BINARY $(SPATZCL_BINARY); \
 		 set VOPTARGS $(VOPTARGS); \
 		 set TESTBENCH $(TBENCH); \
@@ -259,20 +259,30 @@ car-sw-build: chs-sw-build car-sw-all
 
 .PHONY: car-init
 ## Shortcut to initialize carfield with all the targets described above.
-car-init: car-checkout car-hw-init car-sim-init safed-sw-init
+car-init: car-checkout car-hw-init car-sim-init safed-sw-init pulpd-sw-init
 
-# Initialize and build Safety Island SW
-.PHONY: safed-sw-init
+# Initialize and build SW for the Islands
+.PHONY: safed-sw-init pulpd-sw-init
+# Safety Island
 safed-sw-init: $(SAFED_ROOT) $(SAFED_SW_DIR)/pulp-runtime $(SAFED_SW_DIR)/pulp-freertos
 
 $(SAFED_SW_DIR)/pulp-runtime: $(SAFED_ROOT)
 	$(MAKE) -C $(SAFED_ROOT) pulp-runtime
 $(SAFED_SW_DIR)/pulp-freertos: $(SAFED_ROOT)
 	$(MAKE) -C $(SAFED_ROOT) pulp-freertos
 
+# PULP Cluster
+pulpd-sw-init: $(PULPD_ROOT) $(PULPD_ROOT)/pulp-runtime $(PULPD_ROOT)/regression-tests
+
+$(PULPD_ROOT)/pulp-runtime: $(PULPD_ROOT)
+	$(MAKE) -C $(PULPD_ROOT) pulp-runtime
+$(PULPD_ROOT)/regression-tests: $(PULPD_ROOT)
+	$(MAKE) -C $(PULPD_ROOT) regression-tests
+
 # For independent boot of an island, we allow to compile the binary standalone.
-.PHONY: safed-sw-build
-safed-sw-build: safed-sw-init safed-sw-all
+.PHONY: safed-sw-build pulpd-sw-build
+safed-sw-build: safed-sw-all
+pulpd-sw-build: pulpd-sw-all
 
 ############
 # RTL LINT #

diff --git a/hw/carfield.sv b/hw/carfield.sv
@@ -386,8 +386,8 @@ localparam int unsigned IntClusterAxiMstRWidth  =
 // verilog_lint: waive-stop line-length
 
 // External register interface synchronous with Cheshire's clock domain
-carfield_reg_req_t [iomsb(Cfg.RegExtNumSlv-2):0] ext_reg_req;
-carfield_reg_rsp_t [iomsb(Cfg.RegExtNumSlv-2):0] ext_reg_rsp;
+carfield_reg_req_t [iomsb(NumSyncRegSlv):0] ext_reg_req;
+carfield_reg_rsp_t [iomsb(NumSyncRegSlv):0] ext_reg_rsp;
 
 localparam int unsigned LlcIdWidth = Cfg.AxiMstIdWidth   +
                                      $clog2(AxiIn.num_in)+
@@ -505,12 +505,12 @@ logic [                 LogDepth:0] axi_mst_intcluster_r_rptr ;
 carfield_reg2hw_t car_regs_reg2hw;
 carfield_hw2reg_t car_regs_hw2reg;
 
-logic     [NumAsyncRegIdx-1:0] ext_reg_async_slv_req_out;
-logic     [NumAsyncRegIdx-1:0] ext_reg_async_slv_ack_in;
-reg_req_t [NumAsyncRegIdx-1:0] ext_reg_async_slv_data_out;
-logic     [NumAsyncRegIdx-1:0] ext_reg_async_slv_req_in;
-logic     [NumAsyncRegIdx-1:0] ext_reg_async_slv_ack_out;
-reg_rsp_t [NumAsyncRegIdx-1:0] ext_reg_async_slv_data_in;
+logic     [NumAsyncRegSlv-1:0] ext_reg_async_slv_req_out;
+logic     [NumAsyncRegSlv-1:0] ext_reg_async_slv_ack_in;
+reg_req_t [NumAsyncRegSlv-1:0] ext_reg_async_slv_data_out;
+logic     [NumAsyncRegSlv-1:0] ext_reg_async_slv_req_in;
+logic     [NumAsyncRegSlv-1:0] ext_reg_async_slv_ack_out;
+reg_rsp_t [NumAsyncRegSlv-1:0] ext_reg_async_slv_data_in;
 
 // External reg interface slaves (async)
 // Currently for PLL and Padframe
@@ -1175,12 +1175,12 @@ l2_wrap #(
   .slvport_w_data_i    ( axi_slv_ext_w_data  [NumL2Ports-1:0] ),
   .slvport_w_wptr_i    ( axi_slv_ext_w_wptr  [NumL2Ports-1:0] ),
   .slvport_w_rptr_o    ( axi_slv_ext_w_rptr  [NumL2Ports-1:0] ),
-  .l2_ecc_reg_async_mst_req_i  ( ext_reg_async_slv_req_out [L2EccIdx-NumSyncRegIdx] ),
-  .l2_ecc_reg_async_mst_ack_o  ( ext_reg_async_slv_ack_in  [L2EccIdx-NumSyncRegIdx] ),
-  .l2_ecc_reg_async_mst_data_i ( ext_reg_async_slv_data_out[L2EccIdx-NumSyncRegIdx] ),
-  .l2_ecc_reg_async_mst_req_o  ( ext_reg_async_slv_req_in  [L2EccIdx-NumSyncRegIdx] ),
-  .l2_ecc_reg_async_mst_ack_i  ( ext_reg_async_slv_ack_out [L2EccIdx-NumSyncRegIdx] ),
-  .l2_ecc_reg_async_mst_data_o ( ext_reg_async_slv_data_in [L2EccIdx-NumSyncRegIdx] ),
+  .l2_ecc_reg_async_mst_req_i  ( ext_reg_async_slv_req_out [L2EccIdx-NumSyncRegSlv] ),
+  .l2_ecc_reg_async_mst_ack_o  ( ext_reg_async_slv_ack_in  [L2EccIdx-NumSyncRegSlv] ),
+  .l2_ecc_reg_async_mst_data_i ( ext_reg_async_slv_data_out[L2EccIdx-NumSyncRegSlv] ),
+  .l2_ecc_reg_async_mst_req_o  ( ext_reg_async_slv_req_in  [L2EccIdx-NumSyncRegSlv] ),
+  .l2_ecc_reg_async_mst_ack_i  ( ext_reg_async_slv_ack_out [L2EccIdx-NumSyncRegSlv] ),
+  .l2_ecc_reg_async_mst_data_o ( ext_reg_async_slv_data_in [L2EccIdx-NumSyncRegSlv] ),
   .ecc_error_o         ( l2_ecc_err                           )
 );
 
@@ -1376,7 +1376,7 @@ pulp_cluster #(
   .AXI_ID_OUT_WIDTH               ( IntClusterAxiIdOutWidth   ),
   .LOG_DEPTH                      ( LogDepth                  ),
   .BaseAddr                       ( IntClusterBaseAddr        ),
-  .CDC_SYNC_STAGES                ( SyncStages                )
+  .CdcSynchStages                 ( SyncStages                )
 ) i_integer_cluster            (
   .clk_i                       ( pulp_clk                                  ),
   .rst_ni                      ( pulp_rst_n                                ),

diff --git a/hw/carfield_pkg.sv b/hw/carfield_pkg.sv
@@ -137,9 +137,12 @@ typedef enum int {
   PadframeIdx = 'd2, // async
   L2EccIdx    = 'd3  // async
 } cheshire_reg_out_e;
-localparam int unsigned NumSyncRegIdx = PllIdx; // This only works if PllIdx is the first async reg
-localparam int unsigned NumAsyncRegIdx = 3;
-localparam int unsigned NumTotalRegIdx = NumSyncRegIdx + NumAsyncRegIdx;
+localparam int unsigned NumSyncRegSlv = 1;
+                                      // CarRegs
+localparam int unsigned NumAsyncRegSlv =  1  + 1        + 1;
+                                       // PLL  Padframe   L2ECC
+localparam int unsigned NumTotalRegSlv = NumSyncRegSlv + NumAsyncRegSlv;
+localparam int unsigned NumTotalRegRules = NumTotalRegSlv;
 
 typedef enum doub_bt {
   CarRegsBase  = 'h0000_0000_2001_0000,
@@ -273,8 +276,8 @@ localparam cheshire_cfg_t CarfieldCfgDefault = '{
                                                 L2Port2End     ,
                                                 L2Port1End     },
   // External reg slaves (at most 8 ports and rules)
-  RegExtNumSlv      : NumTotalRegIdx,
-  RegExtNumRules    : NumTotalRegIdx,
+  RegExtNumSlv      : NumTotalRegSlv,
+  RegExtNumRules    : NumTotalRegRules,
   // For carfield, PllIdx is the first index of the async reg interfaces. Please add async reg
   // interfaces indices to the left of PllIdx, and sync reg interface indices to its right.
   RegExtRegionIdx   : '{ 0, 0, 0, 0, L2EccIdx,  PadframeIdx,  PllIdx,  CarRegsIdx  },
@@ -412,7 +415,7 @@ localparam int unsigned IntClusterSharedFpuDivSqrt = 0;
 localparam int unsigned IntClusterNumAxiMst = 3;
 localparam int unsigned IntClusterNumAxiSlv = 4;
 // IntClusterAxiIdInWidth is fixed from PULP Cluster
-localparam int unsigned IntClusterAxiIdInWidth = $clog2(IntClusterNumCacheBanks) + 1;
+localparam int unsigned IntClusterAxiIdInWidth = $clog2(IntClusterNumCacheBanks) + 3;
 localparam int unsigned IntClusterAxiIdOutWidth = IntClusterAxiIdInWidth     +
                                                   $clog2(IntClusterNumAxiSlv);
 localparam int unsigned IntClusterMaxUniqId = 1;

diff --git a/hw/cheshire_wrap.sv b/hw/cheshire_wrap.sv
@@ -254,16 +254,16 @@ module cheshire_wrap
   output cheshire_axi_ext_slv_req_t axi_mbox_slv_req_o,
   input  cheshire_axi_ext_slv_rsp_t axi_mbox_slv_rsp_i,
   // External reg demux slaves Cheshire's clock domain (sync)
-  output cheshire_reg_ext_req_t [iomsb(Cfg.RegExtNumSlv-2):0] reg_ext_slv_req_o,
-  input  cheshire_reg_ext_rsp_t [iomsb(Cfg.RegExtNumSlv-2):0] reg_ext_slv_rsp_i,
+  output cheshire_reg_ext_req_t [iomsb(NumSyncRegSlv):0] reg_ext_slv_req_o,
+  input  cheshire_reg_ext_rsp_t [iomsb(NumSyncRegSlv):0] reg_ext_slv_rsp_i,
   // External reg demux slaves other clock domains (async)
   // Padframe and PLL
-  output logic                  [NumAsyncRegIdx-1:0] ext_reg_async_slv_req_o,
-  input  logic                  [NumAsyncRegIdx-1:0] ext_reg_async_slv_ack_i,
-  output cheshire_reg_ext_req_t [NumAsyncRegIdx-1:0] ext_reg_async_slv_data_o,
-  input  logic                  [NumAsyncRegIdx-1:0] ext_reg_async_slv_req_i,
-  output logic                  [NumAsyncRegIdx-1:0] ext_reg_async_slv_ack_o,
-  input  cheshire_reg_ext_rsp_t [NumAsyncRegIdx-1:0] ext_reg_async_slv_data_i,
+  output logic                  [NumAsyncRegSlv-1:0] ext_reg_async_slv_req_o,
+  input  logic                  [NumAsyncRegSlv-1:0] ext_reg_async_slv_ack_i,
+  output cheshire_reg_ext_req_t [NumAsyncRegSlv-1:0] ext_reg_async_slv_data_o,
+  input  logic                  [NumAsyncRegSlv-1:0] ext_reg_async_slv_req_i,
+  output logic                  [NumAsyncRegSlv-1:0] ext_reg_async_slv_ack_o,
+  input  cheshire_reg_ext_rsp_t [NumAsyncRegSlv-1:0] ext_reg_async_slv_data_i,
   // Interrupts from external devices
   input  logic [iomsb(Cfg.NumExtInIntrs):0]                                  intr_ext_i,
   output logic [iomsb(Cfg.NumExtOutIntrTgts):0][iomsb(Cfg.NumExtOutIntrs):0] intr_ext_o,
@@ -347,7 +347,7 @@ cheshire_reg_ext_req_t [iomsb(Cfg.RegExtNumSlv):0] ext_reg_req;
 cheshire_reg_ext_rsp_t [iomsb(Cfg.RegExtNumSlv):0] ext_reg_rsp;
 
 // Generate synchronous external register interface from Cheshire
-for (genvar i = 0; i < NumSyncRegIdx; i++) begin: gen_ext_reg_sync
+for (genvar i = 0; i < NumSyncRegSlv; i++) begin: gen_ext_reg_sync
   assign reg_ext_slv_req_o[i] = ext_reg_req[i];
   assign ext_reg_rsp[i]       = reg_ext_slv_rsp_i[i];
 end
@@ -728,16 +728,16 @@ axi_id_remap            #(
 
 // Async reg interface:
 // See carfield_pkg.sv for indices referring to sync and async reg interfaces.
-for (genvar i = 0; i < Cfg.RegExtNumSlv - NumSyncRegIdx; i++) begin : gen_ext_reg_async
+for (genvar i = 0; i < Cfg.RegExtNumSlv - NumAsyncRegSlv; i++) begin : gen_ext_reg_async
   reg_cdc_src #(
     .CDC_KIND ( "cdc_4phase"              ),
     .req_t     ( cheshire_reg_ext_req_t   ),
     .rsp_t     ( cheshire_reg_ext_rsp_t   )
   ) i_reg_cdc_src (
       .src_clk_i    ( clk_i  ),
       .src_rst_ni   ( rst_ni ),
-      .src_req_i    ( ext_reg_req[NumSyncRegIdx + i] ),
-      .src_rsp_o    ( ext_reg_rsp[NumSyncRegIdx + i] ),
+      .src_req_i    ( ext_reg_req[NumSyncRegSlv + i] ),
+      .src_rsp_o    ( ext_reg_rsp[NumSyncRegSlv + i] ),
 
       .async_req_o  ( ext_reg_async_slv_req_o[i]  ),
       .async_ack_i  ( ext_reg_async_slv_ack_i[i]  ),