AXI-RT: Update to newest version, add simple example

pulp-platform · Sep 21, 2023 · 4a301aa · 4a301aa
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commit 4a301aa
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Showing 20 changed files with 670 additions and 13,182 deletions.
diff --git a/Bender.lock b/Bender.lock
@@ -43,6 +43,15 @@ packages:
     - axi
     - common_cells
     - common_verification
+  axi_rt:
+    revision: b243310dd33b31e4e2ca5229aac20df25cfc45d5
+    version: 0.0.0-alpha
+    source:
+      Git: https://github.com/pulp-platform/axi_rt.git
+    dependencies:
+    - axi
+    - common_cells
+    - register_interface
   axi_vga:
     revision: 07be187d1e954d8090031b32d236ad76dc62ce45
     version: 0.1.1
@@ -108,8 +117,8 @@ packages:
     dependencies:
     - common_cells
   idma:
-    revision: 2c64e0773fab5a54757646715485fcdf3432c7c1
-    version: 0.5.0
+    revision: ca1b28816a3706be0bf9ce01378246d5346384f0
+    version: 0.5.1
     source:
       Git: https://github.com/pulp-platform/iDMA.git
     dependencies:
@@ -136,8 +145,8 @@ packages:
     - register_interface
     - tech_cells_generic
   register_interface:
-    revision: 3b2bf592100b769977c76e51812c55cd742882f6
-    version: 0.4.1
+    revision: d7693be4aef1fc7e7eb2b00b41c42e87d959866c
+    version: 0.4.2
     source:
       Git: https://github.com/pulp-platform/register_interface.git
     dependencies:
@@ -163,15 +172,15 @@ packages:
     - common_cells
     - register_interface
   tech_cells_generic:
-    revision: 298b7297d220ba2601d0f24f684f97ff32f61123
-    version: 0.2.12
+    revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf
+    version: 0.2.13
     source:
       Git: https://github.com/pulp-platform/tech_cells_generic.git
     dependencies:
     - common_verification
   unbent:
-    revision: 791420b326c6455595b4444c02f05f180b99dd06
-    version: 0.1.1
+    revision: 89ea12018002e6fae51f88e25320e79f57db8073
+    version: 0.1.5
     source:
       Git: https://github.com/pulp-platform/unbent.git
     dependencies:

diff --git a/Bender.yml b/Bender.yml
@@ -16,14 +16,15 @@ dependencies:
   axi:                      { git: "https://github.com/pulp-platform/axi.git",                    version: 0.39.0 }
   axi_llc:                  { git: "https://github.com/pulp-platform/axi_llc.git",                version: 0.2.1  }
   axi_riscv_atomics:        { git: "https://github.com/pulp-platform/axi_riscv_atomics.git",      version: 0.8.1  }
+  axi_rt:                   { git: "https://github.com/pulp-platform/axi_rt.git",                 version: 0.0.0-alpha }
   axi_vga:                  { git: "https://github.com/pulp-platform/axi_vga.git",                version: 0.1.1  }
   clint:                    { git: "https://github.com/pulp-platform/clint.git",                  version: 0.2.0  }
   common_cells:             { git: "https://github.com/pulp-platform/common_cells.git",           version: 1.29.0 }
   common_verification:      { git: "https://github.com/pulp-platform/common_verification.git",    version: 0.2.0  }
   cva6:                     { git: "https://github.com/pulp-platform/cva6.git",                   rev: pulp-v0.4.3 }
-  iDMA:                     { git: "https://github.com/pulp-platform/iDMA.git",                   version: 0.5.0  }
+  iDMA:                     { git: "https://github.com/pulp-platform/iDMA.git",                   version: 0.5.1  }
   opentitan_peripherals:    { git: "https://github.com/pulp-platform/opentitan_peripherals.git",  version: 0.4.0  }
-  register_interface:       { git: "https://github.com/pulp-platform/register_interface.git",     version: 0.4.1  }
+  register_interface:       { git: "https://github.com/pulp-platform/register_interface.git",     version: 0.4.2  }
   riscv-dbg:                { git: "https://github.com/pulp-platform/riscv-dbg.git",              version: 0.8.0  }
   serial_link:              { git: "https://github.com/pulp-platform/serial_link.git",            version: 1.1.0  }
   clic:                     { git: "https://github.com/pulp-platform/clic.git",                   version: 2.0.0  }
@@ -34,12 +35,9 @@ export_include_dirs:
   - hw/include
 
 sources:
-  - hw/future/axi_to_reg_v2.sv
   - hw/bootrom/cheshire_bootrom.sv
   - hw/regs/cheshire_reg_pkg.sv
   - hw/regs/cheshire_reg_top.sv
-  - hw/regs/axi_rt_reg_pkg.sv
-  - hw/regs/axi_rt_reg_top.sv
   - hw/cheshire_pkg.sv
   - hw/cheshire_soc.sv
 
@@ -48,6 +46,7 @@ sources:
       - target/sim/models/s25fs512s.v
       - target/sim/models/24FC1025.v
       - target/sim/src/vip_cheshire_soc.sv
+      - target/sim/src/tb_cheshire_pkg.sv
       - target/sim/src/fixture_cheshire_soc.sv
       - target/sim/src/tb_cheshire_soc.sv
 

diff --git a/cheshire.mk b/cheshire.mk
@@ -20,6 +20,7 @@ CHS_LLC_DIR   := $(shell $(BENDER) path axi_llc)
 # Define paths used in dependencies
 OTPROOT      := $(shell $(BENDER) path opentitan_peripherals)
 CLINTROOT    := $(shell $(BENDER) path clint)
+AXIRTROOT    := $(shell $(BENDER) path axi_rt)
 AXI_VGA_ROOT := $(shell $(BENDER) path axi_vga)
 IDMA_ROOT    := $(shell $(BENDER) path idma)
 
@@ -52,7 +53,7 @@ chs-clean-deps:
 ######################
 
 CHS_NONFREE_REMOTE ?= [email protected]:pulp-restricted/cheshire-nonfree.git
-CHS_NONFREE_COMMIT ?= 1c70a67
+CHS_NONFREE_COMMIT ?= 6a5809a
 
 chs-nonfree-init:
 	git clone $(CHS_NONFREE_REMOTE) $(CHS_ROOT)/nonfree
@@ -74,10 +75,6 @@ include $(CHS_ROOT)/sw/sw.mk
 $(CHS_ROOT)/hw/regs/cheshire_reg_pkg.sv $(CHS_ROOT)/hw/regs/cheshire_reg_top.sv: $(CHS_ROOT)/hw/regs/cheshire_regs.hjson
 	$(REGTOOL) -r $< --outdir $(dir $@)
 
-# AXI RT registers
-$(CHS_ROOT)/hw/regs/axi_rt_reg_pkg.sv $(CHS_ROOT)/hw/regs/axi_rt_reg_top.sv: $(CHS_ROOT)/hw/regs/axi_rt_regs.hjson
-	$(REGTOOL) -r $< --outdir $(dir $@)
-
 # CLINT
 CLINTCORES ?= 1
 include $(CLINTROOT)/clint.mk
@@ -89,6 +86,13 @@ include $(OTPROOT)/otp.mk
 $(OTPROOT)/.generated: $(CHS_ROOT)/hw/rv_plic.cfg.hjson
 	flock -x $@ sh -c "cp $< $(dir $@)/src/rv_plic/; $(MAKE) -j1 otp" && touch $@
 
+# AXI RT
+AXIRT_NUM_MGRS ?= 8
+AXIRT_NUM_SUBS ?= 2
+include $(AXIRTROOT)/axirt.mk
+$(AXIRTROOT)/.generated: axirt_regs
+	touch $@
+
 # AXI VGA
 include $(AXI_VGA_ROOT)/axi_vga.mk
 $(AXI_VGA_ROOT)/.generated:
@@ -100,9 +104,9 @@ $(CHS_SLINK_DIR)/.generated: $(CHS_ROOT)/hw/serial_link.hjson
 	flock -x $@ $(MAKE) -C $(CHS_SLINK_DIR) update-regs && touch $@
 
 CHS_HW_ALL += $(CHS_ROOT)/hw/regs/cheshire_reg_pkg.sv $(CHS_ROOT)/hw/regs/cheshire_reg_top.sv
-CHS_HW_ALL += $(CHS_ROOT)/hw/regs/axi_rt_reg_pkg.sv $(CHS_ROOT)/hw/regs/axi_rt_reg_top.sv
 CHS_HW_ALL += $(CLINTROOT)/.generated
 CHS_HW_ALL += $(OTPROOT)/.generated
+CHS_HW_ALL += $(AXIRTROOT)/.generated
 CHS_HW_ALL += $(AXI_VGA_ROOT)/.generated
 CHS_HW_ALL += $(CHS_SLINK_DIR)/.generated
 
@@ -129,7 +133,7 @@ CHS_BOOTROM_ALL += $(CHS_ROOT)/hw/bootrom/cheshire_bootrom.sv $(CHS_ROOT)/hw/boo
 ##############
 
 $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl: Bender.yml
-	$(BENDER) script vsim -t sim -t cv64a6_imafdcsclic_sv39 -t test -t cva6 --vlog-arg="$(VLOG_ARGS)" > $@
+	$(BENDER) script vsim -t sim -t cv64a6_imafdcsclic_sv39 -t test -t cva6 -t rtl --vlog-arg="$(VLOG_ARGS)" > $@
 	echo 'vlog "$(CURDIR)/$(CHS_ROOT)/target/sim/src/elfloader.cpp" -ccflags "-std=c++11"' >> $@
 
 $(CHS_ROOT)/target/sim/models:

diff --git a/docs/tg/sim.md b/docs/tg/sim.md
@@ -21,6 +21,13 @@ We provide a SystemVerilog testbench for `cheshire_soc` running baremetal progra
 
 Preloading boot modes expect an ELF executable to be passed through `BINARY`, while autonomous boot modes expect a disk image (GPT formatted or raw code) to be passed through `IMAGE`. For more information on how to build software for Cheshire and its boot process, see [Software Stack](../um/sw.md).
 
+The `SELCFG` parameter selects the simulation configuration specified in the `tb_cheshire_pkg` package. If not set or set to `0`, the default configuration is selected.
+
+  | `SELCFG` | Configuration (`tb_cheshire_pkg`)                     |
+  | -------- | ----------------------------------------------------- |
+  | 0        | Default configuration from `cheshire_pkg`             |
+  | 1        | AXI-RT-enabled configuration                          |
+
 For simulation of Cheshire in other designs, we provide the module `cheshire_vip` encapsulating all verification IPs and their interfaces. For details, see [Verifying Cheshire In-System](integr.md#verifying-cheshire-in-system).
 
 ## QuestaSim

diff --git a/docs/um/arch.md b/docs/um/arch.md
@@ -41,6 +41,8 @@ Cheshire's internal memory map is *static*. While device instantiation and layou
 |                    | CLINT             | `0x0204_0000` | 256K |       |
 |                    +-------------------+---------------+------+-------+
 |                    | IRQ router        | `0x0208_0000` | 256K |       |
+|                    +-------------------+---------------+------+-------+
+|                    | AXI RT (Cfg)      | `0x020C_0000` | 256K |       |
 +--------------------+-------------------+---------------+------+-------+
 | 4K periphs @ Reg   | SoC Regs          | `0x0300_0000` | 4K   |       |
 |                    +-------------------+---------------+------+-------+
@@ -58,9 +60,7 @@ Cheshire's internal memory map is *static*. While device instantiation and layou
 |                    +-------------------+---------------+------+-------+
 |                    | VGA (Cfg)         | `0x0300_7000` | 4K   |       |
 |                    +-------------------+---------------+------+-------+
-|                    | AXI RT (Cfg)      | `0x0300_8000` | 4K   |       |
-|                    +-------------------+---------------+------+-------+
-|                    | UNBENT            | `0x0300_9000` | 4K   |       |
+|                    | UNBENT            | `0x0300_8000` | 4K   |       |
 +--------------------+-------------------+---------------+------+-------+
 | INTCs @ Reg        | PLIC              | `0x0400_0000` | 64M  |       |
 |                    +-------------------+---------------+------+-------+

diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv
@@ -180,8 +180,10 @@ package cheshire_pkg;
     // Parameters for GPIO
     bit     GpioInputSyncs;
     // Parameters for AXI RT
-    word_bt AxiRtNumPending;
-    word_bt AxiRtWBufferDepth;
+    aw_bt   AxiRtNumPending;
+    dw_bt   AxiRtWBufferDepth;
+    aw_bt   AxiRtNumAddrRegions;
+    bit     AxiRtCutPaths;
   } cheshire_cfg_t;
 
   //////////////////
@@ -263,7 +265,7 @@ package cheshire_pkg;
   localparam doub_bt AmRegs   = 'h0300_0000;
   localparam doub_bt AmLlc    = 'h0300_1000;
   localparam doub_bt AmSlink  = 'h0300_6000;
-  localparam doub_bt AmBusErr = 'h0300_9000;
+  localparam doub_bt AmBusErr = 'h0300_8000;
   localparam doub_bt AmSpm    = 'h1000_0000;  // Cached region at bottom, uncached on top
   localparam doub_bt AmClic   = 'h0800_0000;
 
@@ -400,8 +402,8 @@ package cheshire_pkg;
     if (cfg.Gpio)         begin i++; ret.gpio       = i; r++; ret.map[r] = '{i, 'h0300_5000, 'h0300_6000}; end
     if (cfg.SerialLink)   begin i++; ret.slink      = i; r++; ret.map[r] = '{i, AmSlink, AmSlink +'h1000}; end
     if (cfg.Vga)          begin i++; ret.vga        = i; r++; ret.map[r] = '{i, 'h0300_7000, 'h0300_8000}; end
-    if (cfg.AxiRt)        begin i++; ret.axirt      = i; r++; ret.map[r] = '{i, 'h0300_8000, 'h0300_9000}; end
     if (cfg.IrqRouter)    begin i++; ret.irq_router = i; r++; ret.map[r] = '{i, 'h0208_0000, 'h020c_0000}; end
+    if (cfg.AxiRt)        begin i++; ret.axirt      = i; r++; ret.map[r] = '{i, 'h020c_0000, 'h0210_0000}; end
     if (cfg.Clic) for (int j = 0; j < cfg.NumCores; j++) begin
       i++; ret.clic[j]    = i; r++; ret.map[r] = '{i, AmClic + j*'h40000, AmClic + (j+1)*'h40000};
     end
@@ -590,8 +592,10 @@ package cheshire_pkg;
     // GPIOs
     GpioInputSyncs    : 1,
     // AXI RT
-    AxiRtNumPending   : 16,
-    AxiRtWBufferDepth : 16,
+    AxiRtNumPending     : 16,
+    AxiRtWBufferDepth   : 16,
+    AxiRtNumAddrRegions : 2,
+    AxiRtCutPaths       : 1,
     // All non-set values should be zero
     default: '0
   };

diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv
@@ -1095,86 +1095,45 @@ module cheshire_soc import cheshire_pkg::*; #(
 
   if (Cfg.AxiRt) begin : gen_axi_rt
 
-    // Connect AXI RT units, one for each master
-    axi_rt_reg_pkg::axi_rt_hw2reg_t axi_rt_hw2reg;
-    axi_rt_reg_pkg::axi_rt_reg2hw_t axi_rt_reg2hw;
-
-    // Rule type
-    typedef struct packed {
-      logic [0:0] idx;
-      addr_t      start_addr;
-      addr_t      end_addr;
-    } rt_rule_t;
-
-    localparam rt_rule_t [0:0] RtAddrmap = '{
-      '{ idx: 8'h00, start_addr: '0, end_addr: '1 }
-    };
-
-    for (genvar i = 0; i < AxiIn.num_in; i++) begin : gen_axi_rt_units
-      axi_rt_unit #(
-        .AddrWidth      ( Cfg.AddrWidth     ),
-        .DataWidth      ( Cfg.AxiDataWidth  ),
-        .IdWidth        ( Cfg.AxiMstIdWidth ),
-        .UserWidth      ( Cfg.AxiUserWidth  ),
-        .NumPending     ( Cfg.AxiRtNumPending   ),
-        .WBufferDepth   ( Cfg.AxiRtWBufferDepth ),
-        .NumAddrRegions ( 1  ),
-        .NumRules       ( 1  ),
-        .PeriodWidth    ( 32 ),
-        .BudgetWidth    ( 32 ),
-        .rt_rule_t      ( rt_rule_t ),
-        .addr_t         ( addr_t    ),
-        .aw_chan_t      ( axi_mst_aw_chan_t ),
-        .w_chan_t       ( axi_mst_w_chan_t  ),
-        .axi_req_t      ( axi_mst_req_t ),
-        .axi_resp_t     ( axi_mst_rsp_t )
-      ) i_axi_rt_unit (
-        .clk_i,
-        .rst_ni,
-        .slv_req_i        ( axi_in_req [i] ),
-        .slv_resp_o       ( axi_in_rsp [i] ),
-        .mst_req_o        ( axi_rt_in_req [i] ),
-        .mst_resp_i       ( axi_rt_in_rsp [i] ),
-        .rt_enable_i      ( axi_rt_reg2hw.rt_enable   [i] ),
-        .rt_bypassed_o    ( axi_rt_hw2reg.rt_bypassed [i] ),
-        .len_limit_i      ( axi_rt_reg2hw.len_limit   [i] ),
-        .num_w_pending_o  ( ),
-        .num_aw_pending_o ( ),
-        .rt_rule_i        ( RtAddrmap ),
-        .w_decode_error_o ( ),
-        .r_decode_error_o ( ),
-        .imtu_enable_i    ( axi_rt_reg2hw.imtu_enable [i] ),
-        .imtu_abort_i     ( axi_rt_reg2hw.imtu_abort  [i] ),
-        .w_budget_i       ( axi_rt_reg2hw.write_budget      [i] ),
-        .w_budget_left_o  ( axi_rt_hw2reg.write_budget_left [i] ),
-        .w_period_i       ( axi_rt_reg2hw.write_period      [i] ),
-        .w_period_left_o  ( axi_rt_hw2reg.write_period_left [i] ),
-        .r_budget_i       ( axi_rt_reg2hw.read_budget       [i] ),
-        .r_budget_left_o  ( axi_rt_hw2reg.read_budget_left  [i] ),
-        .r_period_i       ( axi_rt_reg2hw.read_period       [i] ),
-        .r_period_left_o  ( axi_rt_hw2reg.read_period_left  [i] ),
-        .isolate_o        ( axi_rt_hw2reg.isolate  [i] ),
-        .isolated_o       ( axi_rt_hw2reg.isolated [i] )
-      );
-    end
-
-    axi_rt_reg_top #(
-      .reg_req_t  ( reg_req_t ),
-      .reg_rsp_t  ( reg_rsp_t )
-    ) i_axi_rt_regs (
+    axi_rt_unit_top #(
+      .NumManagers      ( AxiIn.num_in  ),
+      .AddrWidth        ( Cfg.AddrWidth ),
+      .DataWidth        ( Cfg.AxiDataWidth  ),
+      .IdWidth          ( Cfg.AxiMstIdWidth ),
+      .UserWidth        ( Cfg.AxiUserWidth  ),
+      .NumPending       ( Cfg.AxiRtNumPending     ),
+      .WBufferDepth     ( Cfg.AxiRtWBufferDepth   ),
+      .NumAddrRegions   ( Cfg.AxiRtNumAddrRegions ),
+      .PeriodWidth      ( 32'd32 ),
+      .BudgetWidth      ( 32'd32 ),
+      .RegIdWidth       ( AxiSlvIdWidth     ),
+      .CutSplitterPaths ( Cfg.AxiRtCutPaths ),
+      .CutDecErrors     ( 1'b0 ),
+      .aw_chan_t        ( axi_mst_aw_chan_t ),
+      .w_chan_t         ( axi_mst_w_chan_t  ),
+      .b_chan_t         ( axi_mst_b_chan_t  ),
+      .ar_chan_t        ( axi_mst_ar_chan_t ),
+      .r_chan_t         ( axi_mst_r_chan_t  ),
+      .axi_req_t        ( axi_mst_req_t ),
+      .axi_resp_t       ( axi_mst_rsp_t ),
+      .req_req_t        ( reg_req_t ),
+      .req_rsp_t        ( reg_rsp_t )
+    ) i_axi_rt_unit_top (
       .clk_i,
       .rst_ni,
+      .slv_req_i  ( axi_in_req    ),
+      .slv_resp_o ( axi_in_rsp    ),
+      .mst_req_o  ( axi_rt_in_req ),
+      .mst_resp_i ( axi_rt_in_rsp ),
       .reg_req_i  ( reg_out_req[RegOut.axirt] ),
       .reg_rsp_o  ( reg_out_rsp[RegOut.axirt] ),
-      .hw2reg     ( axi_rt_hw2reg ),
-      .reg2hw     ( axi_rt_reg2hw ),
-      .devmode_i  ( 1'b1 )
+      .reg_id_i   ( reg_id )
     );
 
   end else begin : gen_no_axi_rt
 
-    assign axi_rt_in_req  = axi_in_req;
-    assign axi_in_rsp     = axi_rt_in_rsp;
+    assign axi_rt_in_req = axi_in_req;
+    assign axi_in_rsp    = axi_rt_in_rsp;
 
   end