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sw: Fix AXI-REALM budget test
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* Fix expected left budget (W/R) calculation
* Extend to support multiple CVA6 cores
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@alex96295
alex96295 committed Oct 22, 2024
1 parent d7ff896 commit 4a1af04
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Showing 3 changed files with 81 additions and 33 deletions.
10 changes: 10 additions & 0 deletions sw/include/params.h
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Expand Up @@ -51,3 +51,13 @@ static const uint64_t __BOOT_DTB_TYPE_GUID[2] = {0x42DE2AEFBA442F61UL, 0x9DCB3A5

// GUID of firmware partition we boot into
static const uint64_t __BOOT_FW_TYPE_GUID[2] = {0x4B0D3F5B99EC86DAUL, 0x59F8A5CFBAC44B8FUL};

// IDs for AXI-REALM managers
// Adjust if more CVA6 cores, default to 1
enum axirealm_mngr_id {
AXIREALM_MNGR_ID_CVA60 = 0,
AXIREALM_MNGR_ID_DBG = 1,
AXIREALM_MNGR_ID_DMA = 2,
AXIREALM_MNGR_ID_SL = 3
};

3 changes: 3 additions & 0 deletions sw/include/util.h
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Expand Up @@ -80,3 +80,6 @@ static inline void *gprw(void *gp) {
if (!(cond)) return (ret);

#define MIN(a, b) (((a) <= (b)) ? (a) : (b))

// Bit manipulation
#define BIT(n) (1UL << (n))
101 changes: 68 additions & 33 deletions sw/tests/axirt_budget.c
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Expand Up @@ -3,60 +3,95 @@
// SPDX-License-Identifier: Apache-2.0
//
// Thomas Benz <[email protected]>
// Alessandro Ottaviano <[email protected]>
//
// Validate the budget functionality of AXI RT

#include "axirt.h"
#include "dif/dma.h"
#include "regs/axi_rt.h"
#include "params.h"
#include "regs/axi_rt.h"
#include "regs/cheshire.h"
#include "util.h"

// transfer
#define SIZE_BYTES 256
#define SRC_STRIDE 0
#define DST_STRIDE 0
#define NUM_REPS 8
#define SRC_ADDR 0x0000000010000000
#define DST_ADDR 0x0000000080000000
#define SIZE_BEAT_BYTES 8
#define DMA_NUM_BEATS 32
#define DMA_NUM_REPS 8
#define DMA_SIZE_BYTES (SIZE_BEAT_BYTES * DMA_NUM_BEATS)
#define DMA_TOTAL_SIZE_BYTES (DMA_SIZE_BYTES * DMA_NUM_REPS)
#define DMA_SRC_STRIDE 0
#define DMA_DST_STRIDE 0
#define SRC_ADDR 0x0000000078000000 // L2
#define DST_ADDR 0x0000000080000000 // DRAM

#define TOTAL_SIZE (SIZE_BYTES * NUM_REPS)
// AXI-REALM
#define CVA6_ALLOCATED_BUDGET 0x10000000
#define CVA6_ALLOCATED_PERIOD 0x10000000
#define DMA_ALLOCATED_BUDGET 0x10000000
#define DMA_ALLOCATED_PERIOD 0x10000000
#define FRAGMENTATION_SIZE_BEATS 1 // Max fragmentation applied to bursts

int main(void) {

uint32_t cheshire_num_harts = *reg32(&__base_regs, CHESHIRE_NUM_INT_HARTS_REG_OFFSET);

// enable and configure axi rt with fragmentation of 8 beats
__axirt_claim(1, 1);
__axirt_set_len_limit_group(7, 0);
__axirt_set_len_limit_group(FRAGMENTATION_SIZE_BEATS, 0);
__axirt_set_len_limit_group(FRAGMENTATION_SIZE_BEATS, 1);
fence();

// configure CVA6
__axirt_set_region(0, 0xffffffff, 0, 0);
__axirt_set_region(0x100000000, 0xffffffffffffffff, 1, 0);
__axirt_set_budget(0x10000000, 0, 0);
__axirt_set_budget(0x10000000, 1, 0);
__axirt_set_period(0x10000000, 0, 0);
__axirt_set_period(0x10000000, 1, 0);
// configure CVA6 cores
for (enum axirealm_mngr_id id = AXIREALM_MNGR_ID_CVA60; id <= cheshire_num_harts; id++) {
__axirt_set_region(0, 0xffffffff, 0, id);
__axirt_set_region(0x100000000, 0xffffffffffffffff, 1, id);
__axirt_set_budget(CVA6_ALLOCATED_BUDGET, 0, id);
__axirt_set_budget(CVA6_ALLOCATED_BUDGET, 1, id);
__axirt_set_period(CVA6_ALLOCATED_PERIOD, 0, id);
__axirt_set_period(CVA6_ALLOCATED_PERIOD, 1, id);
fence();
}

// configure DMA
__axirt_set_region(0, 0xffffffff, 0, 2);
__axirt_set_region(0x100000000, 0xffffffffffffffff, 1, 2);
__axirt_set_budget(0x10000000, 0, 2);
__axirt_set_budget(0x10000000, 1, 2);
__axirt_set_period(0x10000000, 0, 2);
__axirt_set_period(0x10000000, 1, 2);
__axirt_set_region(0, 0xffffffff, 0, AXIREALM_MNGR_ID_DMA);
__axirt_set_region(0x100000000, 0xffffffffffffffff, 1, AXIREALM_MNGR_ID_DMA);
__axirt_set_budget(DMA_ALLOCATED_BUDGET, 0, AXIREALM_MNGR_ID_DMA);
__axirt_set_budget(DMA_ALLOCATED_BUDGET, 1, AXIREALM_MNGR_ID_DMA);
__axirt_set_period(DMA_ALLOCATED_PERIOD, 0, AXIREALM_MNGR_ID_DMA);
__axirt_set_period(DMA_ALLOCATED_PERIOD, 1, AXIREALM_MNGR_ID_DMA);
fence();

// enable RT unit for DMA and CVA6 cores
__axirt_enable((BIT(AXIREALM_MNGR_ID_CVA60) | BIT(AXIREALM_MNGR_ID_DMA)));
fence();

volatile uint64_t *sys_src = (volatile uint64_t *)SRC_ADDR;
volatile uint64_t *sys_dst = (volatile uint64_t *)DST_ADDR;

// initialize src region
for (int i = 0; i < DMA_NUM_BEATS; i++) {
sys_src[i] = 0xcafedeadbaadf00d + i;
fence();
}

// enable RT unit for DMA and CVA6
__axirt_enable(0x5);
// launch blocking DMA transfer
sys_dma_2d_blk_memcpy(DST_ADDR, SRC_ADDR, DMA_SIZE_BYTES, DMA_DST_STRIDE, DMA_SRC_STRIDE, DMA_NUM_REPS);

// launch DMA transfer
sys_dma_2d_blk_memcpy(DST_ADDR, SRC_ADDR, SIZE_BYTES, DST_STRIDE, SRC_STRIDE, NUM_REPS);
// Check DMA transfers against gold.
for (volatile int i = 0; i < DMA_NUM_BEATS; i++) {
CHECK_ASSERT(20, sys_dst[i] == sys_src[i]);
}

// read budget registers and compare
volatile uint32_t read_budget = *reg32(&__base_axirt, AXI_RT_READ_BUDGET_LEFT_2_REG_OFFSET);
volatile uint32_t write_budget = *reg32(&__base_axirt, AXI_RT_WRITE_BUDGET_LEFT_2_REG_OFFSET);
// read budget registers for dma and compare
volatile uint32_t dma_read_budget_left = *reg32(&__base_axirt, AXI_RT_READ_BUDGET_LEFT_4_REG_OFFSET);
volatile uint32_t dma_write_budget_left = *reg32(&__base_axirt, AXI_RT_WRITE_BUDGET_LEFT_4_REG_OFFSET);

// check
volatile uint8_t difference = (TOTAL_SIZE - read_budget) + (TOTAL_SIZE - write_budget);
volatile uint8_t mismatch = read_budget != write_budget;
// check budget: return 0 if (initial budget - final budget) matches number of transferred bytes, otherwise return 1
volatile uint8_t dma_r_difference = (DMA_ALLOCATED_BUDGET - dma_read_budget_left) != DMA_TOTAL_SIZE_BYTES;
volatile uint8_t dma_w_difference = (DMA_ALLOCATED_BUDGET - dma_write_budget_left) != DMA_TOTAL_SIZE_BYTES;
// w and r are symmetric on the dma: left budgets should be equal
volatile uint8_t dma_rw_mismatch = dma_read_budget_left != dma_write_budget_left;

return mismatch | (difference << 1);
return dma_rw_mismatch | dma_r_difference | dma_w_difference;
}

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