Fix CI

Bender.lock

@@ -145,13 +145,8 @@ packages:
     - register_interface
     - tech_cells_generic
   register_interface:
-<<<<<<< HEAD
     revision: d7693be4aef1fc7e7eb2b00b41c42e87d959866c
     version: 0.4.2
-=======
-    revision: ed8c85111db11b8c4b9e37e4f792908e01cea2ba
-    version: null
->>>>>>> 43fe908... Bender.yml: Rollback
     source:
       Git: https://github.com/pulp-platform/register_interface.git
     dependencies:

hw/cheshire_ext_playground.sv

@@ -273,5 +273,5 @@ module cheshire_ext_playground
 //    end
 //  end
   end
- 
+
 endmodule

hw/cheshire_ext_playground_pkg.sv

@@ -16,11 +16,12 @@ package cheshire_ext_playground_pkg;
   // Number of slave peripherals
   localparam int unsigned ChsPlaygndNumPeriphs = 1;
 
-  // Number of slave mems  
+  // Number of slave mems
   localparam int unsigned ChsPlaygndNumAxiMems = 3;
-    
+
   // Total number of master and slaves
-  localparam int unsigned ChsPlaygndNumSlvDevices = ChsPlaygndNumDsaDma + ChsPlaygndNumPeriphs + ChsPlaygndNumAxiMems;
+  localparam int unsigned ChsPlaygndNumSlvDevices = ChsPlaygndNumDsaDma +
+                                                    ChsPlaygndNumPeriphs + ChsPlaygndNumAxiMems;
   localparam int unsigned ChsPlaygndNumMstDevices = ChsPlaygndNumDsaDma;
 
   // Narrow AXI widths
@@ -79,9 +80,12 @@ package cheshire_ext_playground_pkg;
     ret.AxiExtNumSlv      = 5; // For the playground, traffic DMA(s) (config port), system timer
     ret.AxiExtNumRules    = 5;
     // External AXI region map
-    ret.AxiExtRegionIdx   = '{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, MemCoreReadSlvIdx, MemDmaReadSlvIdx, MemWriteSlvIdx, Dsa0SlvIdx, PeriphsSlvIdx };
-    ret.AxiExtRegionStart = '{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, MemCoreReadBase,   MemDmaReadBase,   MemWriteBase,   Dsa0Base,   PeriphsBase   };
-    ret.AxiExtRegionEnd   = '{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, MemCoreReadEnd,    MemDmaReadEnd,    MemWriteEnd,    Dsa0End,    PeriphsEnd    };
+    ret.AxiExtRegionIdx   = '{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, MemCoreReadSlvIdx,
+                              MemDmaReadSlvIdx, MemWriteSlvIdx, Dsa0SlvIdx, PeriphsSlvIdx };
+    ret.AxiExtRegionStart = '{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, MemCoreReadBase,
+                              MemDmaReadBase,   MemWriteBase,   Dsa0Base,   PeriphsBase   };
+    ret.AxiExtRegionEnd   = '{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, MemCoreReadEnd,
+                              MemDmaReadEnd,    MemWriteEnd,    Dsa0End,    PeriphsEnd    };
     ret.BusErr            = 0;
     return ret;
   endfunction

sw/tests/2d_dma.c

@@ -1,3 +1,11 @@
+// Copyright 2023 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Thomas Benz <[email protected]>
+//
+// Playground binary
+
 #include <stdio.h>
 #include <stdlib.h>
 #include <printf.h>
@@ -6,7 +14,7 @@
 #include "axirt.h"
 #include "regs/axi_rt.h"
 
-int main(void){
+int main(void) {
 
     // Size of transfer
     volatile uint64_t size_bytes = 256;

target/sim/vsim/chs_axi_rt_gen_wave.tcl

@@ -1,3 +1,9 @@
+# Copyright 2022 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Thomas Benz <[email protected]>
+
 onerror {resume}
 quietly WaveActivateNextPane {} 0
 set RT_LOC "/tb_cheshire_soc/fix/dut/gen_axi_rt/i_axi_rt_unit_top"

target/sim/vsim/run_pg.tcl

@@ -1,3 +1,9 @@
+# Copyright 2022 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Thomas Benz <[email protected]>
+
 source compile.cheshire_soc.tcl
 set BOOTMODE 0
 set PRELMODE 0