fpga: Testing ddr4

Bender.yml

@@ -47,7 +47,7 @@ sources:
       - target/sim/src/fixture_cheshire_soc.sv
       - target/sim/src/tb_cheshire_soc.sv
 
-  - target: all(fpga, xilinx)
+  - target: any(fpga, xilinx)
     files:
       - target/xilinx/src/fan_ctrl.sv
       - target/xilinx/src/dram_wrapper.sv

cheshire.mk

@@ -55,7 +55,7 @@ chs-clean-deps:
 ######################
 
 CHS_NONFREE_REMOTE ?= [email protected]:pulp-restricted/cheshire-nonfree.git
-CHS_NONFREE_COMMIT ?= e702b4ce754c3b7c9a864a2ce8e2d2fa013056ea
+CHS_NONFREE_COMMIT ?= 65f089e9218084e872009cf1c557965914cacf05
 
 chs-nonfree-init:
 	git clone $(CHS_NONFREE_REMOTE) $(CHS_ROOT)/nonfree
@@ -158,3 +158,4 @@ chs-sim-all: $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl
 #############
 
 include $(CHS_ROOT)/target/xilinx/xilinx.mk
+include $(CHS_XIL_DIR)/sim/simulate.mk

hw/bootrom/cheshire_bootrom.c

@@ -19,6 +19,16 @@
 #include "hal/uart_debug.h"
 #include "gpt.h"
 
+// Todo do this nicer
+#define SPI_OFFSET 1024
+#ifndef SPI_OFFSET
+#define SPI_OFFSET 0
+#endif
+int off_set_spi_sdcard_read_checkcrc(void *priv, void *buf, uint64_t addr, uint64_t len) {
+    return spi_sdcard_read_checkcrc(priv, buf, addr + SPI_OFFSET, len);
+}
+
+
 int boot_passive(uint64_t core_freq) {
     // Initialize UART with debug settings
     uart_debug_init(&__base_uart, core_freq);
@@ -42,7 +52,7 @@ int boot_spi_sdcard(uint64_t core_freq, uint64_t rtc_freq) {
     CHECK_CALL(spi_sdcard_init(&device, core_freq))
     // Wait for device to be initialized (1ms, round up extra tick to be sure)
     clint_spin_until((1000 * rtc_freq) / (1000 * 1000) + 1);
-    return gpt_boot_part_else_raw(spi_sdcard_read_checkcrc, &device, &__base_spm,
+    return gpt_boot_part_else_raw(off_set_spi_sdcard_read_checkcrc, &device, &__base_spm,
                                   __BOOT_SPM_MAX_LBAS, __BOOT_ZSL_TYPE_GUID, 0);
 }
 

sw/tests/helloworld.c

@@ -12,6 +12,23 @@
 #include "dif/uart.h"
 #include "params.h"
 #include "util.h"
+#include "printf.h"
+#include "hal/spi_s25fs512s.h"
+
+
+#define DUMP_SIZE 64
+void dump_spi(spi_s25fs512s_t *device, uint64_t sector) {
+    uint8_t read_buf[512];
+
+    spi_s25fs512s_single_read(device, read_buf, sector*512, 512);
+    for (int i = 0; i < DUMP_SIZE; i++) {
+        if (i % 64 == 0)
+            printf("\r\n%04x : ", sector * 512 + i);
+        printf("%02x", read_buf[i]);
+    }
+    printf("\r\n");
+}
+
 
 int main(void) {
     char str[] = "Hello World!\r\n";
@@ -20,5 +37,31 @@ int main(void) {
     uart_init(&__base_uart, reset_freq, 115200);
     uart_write_str(&__base_uart, str, sizeof(str));
     uart_write_flush(&__base_uart);
+
+    #ifdef TEST_DRAM
+    for(int i = 0; i < 1024*1024*128; i++) {
+        *reg32(&__base_dram, 4*i) = i;
+    }
+    for(int i = 0; i < 1024*1024*128; i++) {
+        if (i != *reg32(&__base_dram, 4*i)) {
+            printf("Error at %x\n", 4*i);
+            return 1;
+        }
+    }
+    #endif
+
+    #ifdef DUMP_SPI
+    spi_s25fs512s_t device = {
+    .spi_freq = MIN(40 * 1000 * 1000, reset_freq / 4), // Up to quarter core freq or 40MHz
+    .csid = 1};
+
+    uint32_t init = spi_s25fs512s_init(&device, reset_freq);
+    printf("Dumping spi : \n\r");
+
+    for (int i = 0; i < 100; i++)
+        dump_spi(&device, i);
+    #endif
+
+    printf("Done\n");
     return 0;
 }

target/xilinx/constraints/cheshire.xdc

@@ -13,21 +13,12 @@
 set_property DONT_TOUCH TRUE [get_cells i_sys_clk_div/i_clk_bypass_mux]
 
 # The net of which we get the 200 MHz single ended clock from the MIG
-set MIG_CLK_SRC [get_pins -filter {DIRECTION == OUT} -leaf -of_objects [get_nets dram_clock_out]]
-set MIG_RST_SRC [get_pins -filter {DIRECTION == OUT} -leaf -of_objects [get_nets dram_sync_reset]]
-
 set SOC_RST_SRC [get_pins -filter {DIRECTION == OUT} -leaf -of_objects [get_nets rst_n]]
 
 #####################
 # Timing Parameters #
 #####################
 
-# 333 MHz (max) DRAM Axi clock
-set FPGA_TCK 3.0
-
-# 200 MHz DRAM Generated clock
-set DRAM_TCK 5.0
-
 # 50 MHz SoC clock
 set SOC_TCK 20.0
 
@@ -44,8 +35,15 @@ set UART_IO_SPEED 200.0
 # Clocks #
 ##########
 
+# Clk_wiz clocks
+create_clock -period 100 -name clk_10 [get_pins i_xlnx_clk_wiz/clk_10]
+create_clock -period 50 -name clk_20 [get_pins i_xlnx_clk_wiz/clk_20]
+create_clock -period 20 -name clk_50 [get_pins i_xlnx_clk_wiz/clk_50]
+create_clock -period 10 -name clk_100 [get_pins i_xlnx_clk_wiz/clk_100]
+
 # System Clock
-create_generated_clock -name clk_soc -source $MIG_CLK_SRC -divide_by 4 [get_nets soc_clk]
+# [see in board.xdc]
+
 # JTAG Clock
 create_clock -period $JTAG_TCK -name clk_jtag [get_ports jtag_tck_i]
 set_input_jitter clk_jtag 1.000
@@ -55,14 +53,7 @@ set_input_jitter clk_jtag 1.000
 ################
 
 # JTAG Clock is asynchronous to all other clocks
-set_clock_groups -name jtag_async -asynchronous -group [get_clocks clk_jtag]
-
-#######################
-# Placement Overrides #
-#######################
-
-# Accept suboptimal BUFG-BUFG cascades
-set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_sys_clk_div/i_clk_mux/clk0_i]
+set_clock_groups -name jtag_async -asynchronous -group {clk_jtag}
 
 ########
 # JTAG #
@@ -77,13 +68,6 @@ set_output_delay -max -clock clk_jtag [expr 0.20 * $JTAG_TCK] [get_ports jtag_td
 set_max_delay  -from [get_ports jtag_trst_ni] $JTAG_TCK
 set_false_path -hold -from [get_ports jtag_trst_ni]
 
-#######
-# MIG #
-#######
-
-set_max_delay  -from $MIG_RST_SRC $FPGA_TCK
-set_false_path -hold -from $MIG_RST_SRC
-
 ########
 # UART #
 ########
@@ -101,15 +85,6 @@ set_false_path -hold -to [get_ports uart_tx_o]
 # cdc_fifo_gray: Disable hold checks, limit datapath delay and bus skew
 set_property KEEP_HIERARCHY SOFT [get_cells i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*i_sync]
 set_false_path -hold -through [get_pins -of_objects [get_cells i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*]] -through [get_pins -of_objects [get_cells i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*]]
-set_max_delay -datapath -from [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_dst_*/*i_sync/reg*/D] $FPGA_TCK
-set_max_delay -datapath -from [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_src_*/*i_sync/reg*/D] $FPGA_TCK
-set_max_delay -datapath -from [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] $FPGA_TCK
-
-###################
-# Reset Generator #
-###################
-
-set_max_delay -from $SOC_RST_SRC $SOC_TCK
-set_false_path -hold -from $SOC_RST_SRC
 
-set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets i_xlnx_clk_wiz/inst/clkin1_ibufds/O]
+set_false_path -hold -through [get_pins -of_objects [get_cells -hier -filter {ORIG_REF_NAME == axi_cdc_src || REF_NAME == axi_cdc_src}] -filter {NAME =~ *async*}]
+set_false_path -hold -through [get_pins -of_objects [get_cells -hier -filter {ORIG_REF_NAME == axi_cdc_dst || REF_NAME == axi_cdc_dst}] -filter {NAME =~ *async*}]

target/xilinx/constraints/genesys2.xdc

@@ -5,6 +5,29 @@
 # Testmode is set to 0 during normal use
 set_case_analysis 0 [get_ports testmode_i]
 
+
+set all_in_mux [get_nets -of [ get_pins -filter { DIRECTION == IN } -of [get_cells -hier -filter { ORIG_REF_NAME == tc_clk_mux2 || REF_NAME == tc_clk_mux2 }]]]
+set_property CLOCK_DEDICATED_ROUTE FALSE $all_in_mux
+set_property CLOCK_BUFFER_TYPE NONE $all_in_mux
+
+#############
+# Sys clock #
+#############
+
+create_clock -period 5 -name sys_clk [get_pins u_ibufg_sys_clk/O]
+set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins u_ibufg_sys_clk/O]
+set_clock_groups -name sys_clk_async -asynchronous -group {sys_clk}
+
+
+#############
+# Mig clock #
+#############
+
+set MIG_RST [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst]
+create_clock -period 5 -name dram_axi_clk [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk]
+set_false_path -hold -through $MIG_RST
+set_max_delay -through $MIG_RST 5 
+
 #######
 # VGA #
 #######
@@ -54,8 +77,8 @@ set_false_path -hold -to [get_ports {i2c_scl_io i2c_sda_io}]
 ###############
 
 ## Clock Signal
-# set_property -dict { PACKAGE_PIN AD11  IOSTANDARD LVDS     } [get_ports { sysclk_n }]; #IO_L12N_T1_MRCC_33 Sch=sysclk_n
-# set_property -dict { PACKAGE_PIN AD12  IOSTANDARD LVDS     } [get_ports { sysclk_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p
+set_property -dict { PACKAGE_PIN AD11  IOSTANDARD LVDS     } [get_ports { sys_clk_n }]; #IO_L12N_T1_MRCC_33 Sch=sysclk_n
+set_property -dict { PACKAGE_PIN AD12  IOSTANDARD LVDS     } [get_ports { sys_clk_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p
 
 ## Buttons
 #set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS12 } [get_ports { btnc }]; #IO_25_17 Sch=btnc

target/xilinx/constraints/vcu128.xdc

@@ -6,6 +6,35 @@
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_ports jtag_tck_i]]
 set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_ports jtag_tck_i]]
 
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_ports cpu_reset]]
+set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_ports cpu_reset]]
+
+set all_in_mux [get_nets -of [ get_pins -filter { DIRECTION == IN } -of [get_cells -hier -filter { ORIG_REF_NAME == tc_clk_mux2 || REF_NAME == tc_clk_mux2 }]]]
+set_property CLOCK_DEDICATED_ROUTE FALSE $all_in_mux
+set_property CLOCK_BUFFER_TYPE NONE $all_in_mux
+
+#############
+# Sys clock #
+#############
+
+create_clock -period 10 -name sys_clk [get_pins u_ibufg_sys_clk/O]
+set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins u_ibufg_sys_clk/O]
+set_clock_groups -name sys_clk_async -asynchronous -group {sys_clk}
+
+#############
+# Mig clock #
+#############
+
+set MIG_RST [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst]
+#create_clock -period 10 -name dram_axi_clk [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk]
+set_false_path -hold -through $MIG_RST
+set_max_delay -through $MIG_RST 10
+
+set_max_delay -datapath -from [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_dst_*/*i_sync/reg*/D] $FPGA_TCK
+set_max_delay -datapath -from [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] $FPGA_TCK
+
+
+
 #################################################################################
 
 ###############

target/xilinx/constraints/zcu102.xdc

@@ -1,3 +1,31 @@
+##############################
+# BOARD SPECIFIC CONSTRAINTS #
+##############################
+
+#############
+# Sys clock #
+#############
+
+create_clock -period 8 -name sys_clk [get_pins u_ibufg_sys_clk/O]
+set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins u_ibufg_sys_clk/O]
+set_clock_groups -name sys_clk_async -asynchronous -group {sys_clk}
+
+#############
+# Mig clock #
+#############
+
+set MIG_RST [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst]
+create_clock -period 8 -name dram_axi_clk [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk]
+set_false_path -hold -through $MIG_RST
+set_max_delay -through $MIG_RST 8
+
+
+#################################################################################
+
+###############
+# ASSIGN PINS #
+###############
+
 #################################################
 ### ZCU102 Rev1.0 Master XDC file 09-15-2016 ####
 #################################################
@@ -183,10 +211,10 @@ set_property IOSTANDARD  LVCMOS33 [get_ports "jtag_tck_i"] ;# Bank  47 VCCO - VC
 #set_property IOSTANDARD  LVCMOS33 [get_ports "PMOD1_4"] ;# Bank  47 VCCO - VCC3V3   - IO_L6N_HDGC_AD6N_47
 #set_property PACKAGE_PIN G20      [get_ports "PMOD1_5"] ;# Bank  47 VCCO - VCC3V3   - IO_L6P_HDGC_AD6P_47
 #set_property IOSTANDARD  LVCMOS33 [get_ports "PMOD1_5"] ;# Bank  47 VCCO - VCC3V3   - IO_L6P_HDGC_AD6P_47
-#set_property PACKAGE_PIN F21      [get_ports "CLK_125_N"] ;# Bank  47 VCCO - VCC3V3   - IO_L5N_HDGC_AD7N_47
-#set_property IOSTANDARD  LVDS_25  [get_ports "CLK_125_N"] ;# Bank  47 VCCO - VCC3V3   - IO_L5N_HDGC_AD7N_47
-#set_property PACKAGE_PIN G21      [get_ports "CLK_125_P"] ;# Bank  47 VCCO - VCC3V3   - IO_L5P_HDGC_AD7P_47
-#set_property IOSTANDARD  LVDS_25  [get_ports "CLK_125_P"] ;# Bank  47 VCCO - VCC3V3   - IO_L5P_HDGC_AD7P_47
+set_property PACKAGE_PIN F21      [get_ports "sys_clk_n"] ;# Bank  47 VCCO - VCC3V3   - IO_L5N_HDGC_AD7N_47 -> CLK_125_N
+set_property IOSTANDARD  LVDS_25  [get_ports "sys_clk_n"] ;# Bank  47 VCCO - VCC3V3   - IO_L5N_HDGC_AD7N_47 -> CLK_125_N
+set_property PACKAGE_PIN G21      [get_ports "sys_clk_p"] ;# Bank  47 VCCO - VCC3V3   - IO_L5P_HDGC_AD7P_47 -> CLK_125_P
+set_property IOSTANDARD  LVDS_25  [get_ports "sys_clk_p"] ;# Bank  47 VCCO - VCC3V3   - IO_L5P_HDGC_AD7P_47 -> CLK_125_P
 #set_property PACKAGE_PIN J20      [get_ports "PMOD1_6"] ;# Bank  47 VCCO - VCC3V3   - IO_L4N_AD8N_47
 #set_property IOSTANDARD  LVCMOS33 [get_ports "PMOD1_6"] ;# Bank  47 VCCO - VCC3V3   - IO_L4N_AD8N_47
 #set_property PACKAGE_PIN J19      [get_ports "PMOD1_7"] ;# Bank  47 VCCO - VCC3V3   - IO_L4P_AD8P_47

target/xilinx/sim/run_simulation.tcl

@@ -6,8 +6,11 @@
 
 #source ips/xlnx_mig_7_ddr3_ex/questa/compile.do
 #source ips/xlnx_mig_7_ddr3/questa/compile.do
-source ips/xlnx_mig_ddr4_ex/questa/compile.do
-source ips/xlnx_mig_ddr4/questa/compile.do
+
+#source ips/xlnx_mig_ddr4_ex/questa/compile.do
+#source ips/xlnx_mig_ddr4/questa/compile.do
+#source ips/xlnx_clk_wiz/questa/compile.do
+#source ips/xlnx_vio/questa/compile.do
 source ../scripts/add_sources_vsim.tcl
 
 

target/xilinx/sim/simulate.mk

@@ -4,11 +4,13 @@
 #
 # Cyril Koenig <[email protected]>
 
+CHS_XIL_SIM_DIR  ?= $(CHS_XIL_DIR)/sim
+
 XILINX_SIMLIB_PATH ?= ~/xlib_questa-2022.3_vivado-2022.1
 SIMULATOR_PATH ?= /usr/pack/questa-2022.3-bt/questasim/bin
 GCC_PATH ?= /usr/pack/questa-2022.3-bt/questasim/gcc-7.4.0-linux_x86_64/bin
 
-ip-sim-scripts := $(addsuffix /questa/compile.do, $(addprefix sim/ips/, $(ips-names)))
+ip-sim-scripts := $(addsuffix /questa/compile.do, $(addprefix $(CHS_XIL_SIM_DIR)/ips/, $(ips-names)))
 
 # Pre-generated/modified example projects (contain the simulation top level)
 ifeq ($(BOARD),vcu128)
@@ -18,37 +20,37 @@ ifeq ($(BOARD),genesys2)
 	ip-example-projects := xlnx_mig_7_ddr3_ex
 endif
 
-ip-example-sim-scripts := $(addsuffix /questa/compile.do, $(addprefix sim/ips/, $(ip-example-projects)))
+ip-example-sim-scripts := $(addsuffix /questa/compile.do, $(addprefix $(CHS_XIL_SIM_DIR)/ips/, $(ip-example-projects)))
 
 VIVADOENV_SIM := $(VIVADOENV) \
               XILINX_SIMLIB_PATH=$(XILINX_SIMLIB_PATH) \
               SIMULATOR_PATH=$(SIMULATOR_PATH) \
 			  GCC_PATH=$(GCC_PATH) \
-			  VIVADO_PROJECT=../${PROJECT}.xpr
+			  VIVADO_PROJECT=$(CHS_XIL_DIR)/${PROJECT}.xpr
 VLOG_ARGS := -suppress 2583 -suppress 13314
 
 # Fetch example projects at IIS (containing SRAM behavioral models)
-sim/ips/%_ex/questa/compile.do:
-	tar -xvf /usr/scratch2/wuerzburg/cykoenig/export/$*_ex.tar -C sim/ips
+$(CHS_XIL_SIM_DIR)/ips/%_ex/questa/compile.do:
+	tar -xvf /usr/scratch2/wuerzburg/cykoenig/export/$*_ex.tar -C $(CHS_XIL_SIM_DIR)/ips
 
 # Generate simulation libraries
 $(XILINX_SIMLIB_PATH)/modelsim.ini:
-	cd sim && $(VIVADOENV_SIM) vitis-2022.1 vivado -nojournal -mode batch -source setup_simulation.tcl -tclargs "compile_simlib"
+	cd $(CHS_XIL_SIM_DIR) && $(VIVADOENV_SIM) vitis-2022.1 vivado -nojournal -mode batch -source setup_simulation.tcl -tclargs "compile_simlib"
 
 # 
-sim/ips/%/questa/compile.do:
-	cd sim && $(VIVADOENV_SIM) $(VIVADO) -nojournal -mode batch -source setup_simulation.tcl -tclargs "export_simulation"
+$(CHS_XIL_SIM_DIR)/ips/%/questa/compile.do:
+	cd $(CHS_XIL_SIM_DIR) && $(VIVADOENV_SIM) $(VIVADO) -nojournal -mode batch -source setup_simulation.tcl -tclargs "export_simulation"
 
-scripts/add_sources_vsim.tcl:
-	$(BENDER) script vsim -t sim -t test -t fpga -t cv64a6_imafdcsclic_sv39 -t cva6 $(bender-targets) --vlog-arg="$(VLOG_ARGS)" > $@
+$(CHS_XIL_DIR)/scripts/add_sources_vsim.tcl:
+	$(BENDER) script vsim -t sim -t test $(xilinx_targs) --vlog-arg="$(VLOG_ARGS)" > $@
 
-sim: ${PROJECT}.xpr $(XILINX_SIMLIB_PATH)/modelsim.ini $(ip-example-sim-scripts) $(ip-sim-scripts) scripts/add_sources_vsim.tcl
-	mkdir -p sim/questa_lib
-	cp $(XILINX_SIMLIB_PATH)/modelsim.ini sim
-	chmod +w sim/modelsim.ini
-	cd sim && questa-2022.3 vsim -work work -do "run_simulation.tcl"
+chs-xil-sim: $(CHS_XIL_DIR)/${PROJECT}.xpr $(XILINX_SIMLIB_PATH)/modelsim.ini $(ip-example-sim-scripts) $(ip-sim-scripts) $(CHS_XIL_DIR)/scripts/add_sources_vsim.tcl
+	mkdir -p $(CHS_XIL_SIM_DIR)/questa_lib
+	cp $(XILINX_SIMLIB_PATH)/modelsim.ini $(CHS_XIL_SIM_DIR)
+	chmod +w $(CHS_XIL_SIM_DIR)/modelsim.ini
+	cd $(CHS_XIL_SIM_DIR) && questa-2022.3 vsim -work work -do "run_simulation.tcl"
 
-clean-sim:
-	rm -rf sim/*.log sim/questa_lib sim/work sim/transcript sim/vsim.wlf scripts/vsim_cheshire.tcl sim/.Xil sim/modelsim.ini
+chs-xil-clean-sim:
+	cd $(CHS_XIL_DIR) && rm -rf sim/*.log sim/questa_lib sim/work sim/transcript sim/vsim.wlf scripts/vsim_cheshire.tcl sim/.Xil sim/modelsim.ini
 
 .PHONY: clean-sim sim