Attempt to fix System Verilog lint.

pulp-platform · Dec 5, 2023 · 41dd7d5 · 41dd7d5
1 parent 44083f6
commit 41dd7d5
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv
@@ -610,7 +610,7 @@ module cheshire_soc import cheshire_pkg::*; #(
   if (Cfg.HmrUnit == 1) begin : gen_hmr_unit_reg_intf
     assign reg_out_core_req = reg_out_req[RegOut.hmr_unit];
     assign reg_out_rsp[RegOut.hmr_unit] = reg_out_core_rsp;
-  end else begin
+  end else begin : gen_no_hmr_unit_reg_intf
     assign reg_out_core_req = '0;
   end