target/sim: Add DRAMSys main memory option (#136)

* target/sim: Add DRAMSys as main mem option Signed-off-by: Nils Wistoff <[email protected]> * ci: Bump cheshire-nonfree Signed-off-by: Nils Wistoff <[email protected]> * Bump dramsys Signed-off-by: Nils Wistoff <[email protected]> * target/sim: Minor cleanup * target/sim: Document DRAMSys, remove from default build path * target/sim: Make target `chs-dramsys-all` phony Signed-off-by: Nils Wistoff <[email protected]> --------- Signed-off-by: Nils Wistoff <[email protected]> Co-authored-by: Paul Scheffler <[email protected]>
pulp-platform · Sep 9, 2024 · 413cb80 · 413cb80
1 parent 99dd957
commit 413cb80
Show file tree

Hide file tree

Showing 10 changed files with 136 additions and 47 deletions.
diff --git a/.gitignore b/.gitignore
@@ -28,6 +28,7 @@ sw/deps/.patched
 
 # Test models
 target/sim/models
+target/sim/dramsys
 
 # VSIM generated files
 target/sim/vsim/compile.*.tcl

diff --git a/Bender.lock b/Bender.lock
@@ -101,6 +101,13 @@ packages:
     - common_cells
     - fpnew
     - tech_cells_generic
+  dram_rtl_sim:
+    revision: 2cac4a9e12a60537567276b539ab6c919c87b5dc
+    version: 0.1.1
+    source:
+      Git: https://github.com/pulp-platform/dram_rtl_sim.git
+    dependencies:
+    - axi
   fpnew:
     revision: f231041c610f270ffc03cbdac38739ddb6426572
     version: null

diff --git a/Bender.yml b/Bender.yml
@@ -30,6 +30,7 @@ dependencies:
   riscv-dbg:                { git: "https://github.com/pulp-platform/riscv-dbg.git",              version: 0.8.1  }
   serial_link:              { git: "https://github.com/pulp-platform/serial_link.git",            version: 1.1.1  }
   unbent:                   { git: "https://github.com/pulp-platform/unbent.git",                 version: 0.1.6  }
+  dram_rtl_sim:             { git: "https://github.com/pulp-platform/dram_rtl_sim.git",           version: 0.1.1  }
 
 export_include_dirs:
   - hw/include

diff --git a/cheshire.mk b/cheshire.mk
@@ -8,7 +8,10 @@
 
 BENDER ?= bender
 
-VLOG_ARGS ?= -suppress 2583 -suppress 13314
+# Caution: Questasim requires this to point to the *actual* compiler install path
+CXX_PATH := $(shell which $(CXX))
+
+VLOG_ARGS ?= -suppress 2583 -suppress 13314 -timescale 1ns/1ps
 VSIM      ?= vsim
 
 # Define used paths (prefixed to avoid name conflicts)
@@ -18,11 +21,12 @@ CHS_SLINK_DIR := $(shell $(BENDER) path serial_link)
 CHS_LLC_DIR   := $(shell $(BENDER) path axi_llc)
 
 # Define paths used in dependencies
-OTPROOT      := $(shell $(BENDER) path opentitan_peripherals)
-CLINTROOT    := $(shell $(BENDER) path clint)
-AXIRTROOT    := $(shell $(BENDER) path axi_rt)
-AXI_VGA_ROOT := $(shell $(BENDER) path axi_vga)
-IDMA_ROOT    := $(shell $(BENDER) path idma)
+OTPROOT           := $(shell $(BENDER) path opentitan_peripherals)
+CLINTROOT         := $(shell $(BENDER) path clint)
+AXIRTROOT         := $(shell $(BENDER) path axi_rt)
+AXI_VGA_ROOT      := $(shell $(BENDER) path axi_vga)
+IDMA_ROOT         := $(shell $(BENDER) path idma)
+DRAM_RTL_SIM_ROOT := $(shell $(BENDER) path dram_rtl_sim)
 
 REGTOOL ?= $(CHS_REG_DIR)/vendor/lowrisc_opentitan/util/regtool.py
 
@@ -46,14 +50,15 @@ endif
 # Running this target will reset dependencies (without updating the checked-in Bender.lock)
 chs-clean-deps:
 	rm -rf .bender
-	cd $(CHS_ROOT) && git submodule deinit -f sw/deps/printf
+	cd $(CHS_ROOT) && rm -rf target/sim/models target/sim/dramsys
+	cd $(CHS_ROOT) && git submodule deinit -f sw/deps/*
 
 ######################
 # Nonfree components #
 ######################
 
 CHS_NONFREE_REMOTE ?= [email protected]:pulp-restricted/cheshire-nonfree.git
-CHS_NONFREE_COMMIT ?= cba34e2
+CHS_NONFREE_COMMIT ?= f731b17
 
 chs-nonfree-init:
 	git clone $(CHS_NONFREE_REMOTE) $(CHS_ROOT)/nonfree
@@ -134,7 +139,7 @@ CHS_BOOTROM_ALL += $(CHS_ROOT)/hw/bootrom/cheshire_bootrom.sv $(CHS_ROOT)/hw/boo
 
 $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl: $(CHS_ROOT)/Bender.yml
 	$(BENDER) script vsim -t sim -t cv64a6_imafdcsclic_sv39 -t test -t cva6 -t rtl --vlog-arg="$(VLOG_ARGS)" > $@
-	echo 'vlog "$(realpath $(CHS_ROOT))/target/sim/src/elfloader.cpp" -ccflags "-std=c++11"' >> $@
+	echo 'vlog "$(realpath $(CHS_ROOT))/target/sim/src/elfloader.cpp" -ccflags "-std=c++11" -cpppath "$(CXX_PATH)"' >> $@
 
 .PRECIOUS: $(CHS_ROOT)/target/sim/models
 $(CHS_ROOT)/target/sim/models:
@@ -155,6 +160,15 @@ CHS_SIM_ALL += $(CHS_ROOT)/target/sim/models/s25fs512s.v
 CHS_SIM_ALL += $(CHS_ROOT)/target/sim/models/24FC1025.v
 CHS_SIM_ALL += $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl
 
+###########
+# DRAMSys #
+###########
+
+DRAMSYS_ROOT ?= $(CHS_ROOT)/target/sim/dramsys
+include $(DRAM_RTL_SIM_ROOT)/dram_rtl_sim.mk
+
+CHS_DRAMSYS_ALL += $(DRAMSYS_ROOT)/build/lib/libsystemc.so
+
 #############
 # FPGA Flow #
 #############
@@ -165,7 +179,7 @@ include $(CHS_ROOT)/target/xilinx/xilinx.mk
 # Phonies (KEEP AT END OF FILE) #
 #################################
 
-.PHONY: chs-all chs-nonfree-init chs-clean-deps chs-sw-all chs-hw-all chs-bootrom-all chs-sim-all chs-xilinx-all
+.PHONY: chs-all chs-nonfree-init chs-clean-deps chs-sw-all chs-hw-all chs-bootrom-all chs-sim-all chs-dramsys-all chs-xilinx-all
 
 CHS_ALL += $(CHS_SW_ALL) $(CHS_HW_ALL) $(CHS_SIM_ALL)
 
@@ -174,4 +188,5 @@ chs-sw-all:      $(CHS_SW_ALL)
 chs-hw-all:      $(CHS_HW_ALL)
 chs-bootrom-all: $(CHS_BOOTROM_ALL)
 chs-sim-all:     $(CHS_SIM_ALL)
+chs-dramsys-all: $(CHS_DRAMSYS_ALL)
 chs-xilinx-all:  $(CHS_XILINX_ALL)
diff --git a/docs/gs.md b/docs/gs.md
@@ -20,6 +20,7 @@ The project is structured as follows:
 To *build* Cheshire, you will need:
 
 - GNU Make `>= 3.82`
+- CMake `>=3.24.0`
 - Python `>= 3.9`
 - Bender `>= 0.27.1`
 - RISCV GCC `>= 11.2.0`
@@ -56,6 +57,7 @@ The following additional targets are not invoked by the above, but also availabl
 - `bootrom-all`: Rebuilds the boot ROM. This is not done by default as reproducible builds (as checked by CI) can only be guaranteed for fixed compiler versions.
 - `nonfree-init`: Clones our internal repository with nonfree resources we cannot release, including our internal CI. *This is not necessary to use Cheshire*.
 - `clean-deps`: Removes checked-out bender dependencies and submodules. This is useful when references to dependencies are updated.
+- `dramsys-all`: Builds [DRAMSys-based DRAM Simulation](https://github.com/pulp-platform/dram_rtl_sim) for Cheshire's simulation targets; see [Testbench](tg/sim.md#DramSys).
 
 ## Targets
 

diff --git a/docs/tg/sim.md b/docs/tg/sim.md
@@ -21,13 +21,15 @@ We provide a SystemVerilog testbench for `cheshire_soc` running baremetal progra
 
 Preloading boot modes expect an ELF executable to be passed through `BINARY`, while autonomous boot modes expect a disk image (GPT formatted or raw code) to be passed through `IMAGE`. For more information on how to build software for Cheshire and its boot process, see [Software Stack](../um/sw.md).
 
-The `SELCFG` parameter selects the simulation configuration specified in the `tb_cheshire_pkg` package. If not set or set to `0`, the default configuration is selected.
+The `SELCFG` environment variable selects the Cheshire configuration used in simulations. Possible configurations are specified in the `tb_cheshire_pkg` package. If not set or set to `0`, the default configuration is selected.
 
-| `SELCFG` | Configuration (`tb_cheshire_pkg`)         |
+| `SELCFG` | Configuration in (`tb_cheshire_pkg`)      |
 | -------- | ----------------------------------------- |
 | 0        | Default configuration from `cheshire_pkg` |
 | 1        | AXI-RT-enabled configuration              |
 
+The `USE_DRAMSYS` environment variable controls whether simulations are linked against and use DRAMSys for DRAM simulation. Note that before starting a simulation using DRAMSys, it must be built with `make chs-dramsys-all` first.
+
 For simulation of Cheshire in other designs, we provide the module `cheshire_vip` encapsulating all verification IPs and their interfaces. For details, see [Verifying Cheshire In-System](integr.md#verifying-cheshire-in-system).
 
 ## QuestaSim

diff --git a/target/sim/src/fixture_cheshire_soc.sv b/target/sim/src/fixture_cheshire_soc.sv
@@ -8,7 +8,8 @@
 
 module fixture_cheshire_soc #(
   /// The selected simulation configuration from the `tb_cheshire_pkg`.
-  parameter int unsigned SelectedCfg = 32'd0
+  parameter int unsigned SelectedCfg = 32'd0,
+  parameter bit          UseDramSys  = 1'b0
 );
 
   `include "cheshire/typedef.svh"
@@ -168,6 +169,7 @@ module fixture_cheshire_soc #(
 
   vip_cheshire_soc #(
     .DutCfg            ( DutCfg ),
+    .UseDramSys        ( UseDramSys ),
     .axi_ext_llc_req_t ( axi_llc_req_t ),
     .axi_ext_llc_rsp_t ( axi_llc_rsp_t ),
     .axi_ext_mst_req_t ( axi_mst_req_t ),

diff --git a/target/sim/src/tb_cheshire_soc.sv b/target/sim/src/tb_cheshire_soc.sv
@@ -7,10 +7,14 @@
 
 module tb_cheshire_soc #(
   /// The selected simulation configuration from the `tb_cheshire_pkg`.
-  parameter int unsigned SelectedCfg = 32'd0
+  parameter int unsigned SelectedCfg = 32'd0,
+  parameter bit          UseDramSys  = 1'b0
 );
 
-  fixture_cheshire_soc #(.SelectedCfg(SelectedCfg)) fix();
+  fixture_cheshire_soc #(
+    .SelectedCfg  (SelectedCfg),
+    .UseDramSys   (UseDramSys)
+  ) fix();
 
   string      preload_elf;
   string      boot_hex;

diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv
@@ -12,6 +12,7 @@
 module vip_cheshire_soc import cheshire_pkg::*; #(
   // DUT (must be set)
   parameter cheshire_cfg_t DutCfg           = '0,
+  parameter bit           UseDramSys        = 0,
   parameter type          axi_ext_llc_req_t = logic,
   parameter type          axi_ext_llc_rsp_t = logic,
   parameter type          axi_ext_mst_req_t = logic,
@@ -92,37 +93,67 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
   //  DRAM  //
   ////////////
 
-  axi_sim_mem #(
-    .AddrWidth          ( DutCfg.AddrWidth    ),
-    .DataWidth          ( DutCfg.AxiDataWidth ),
-    .IdWidth            ( $bits(axi_llc_id_t) ),
-    .UserWidth          ( DutCfg.AxiUserWidth ),
-    .axi_req_t          ( axi_llc_req_t ),
-    .axi_rsp_t          ( axi_llc_rsp_t ),
-    .WarnUninitialized  ( 0 ),
-    .ClearErrOnAccess   ( 1 ),
-    .ApplDelay          ( ClkPeriodSys * TAppl ),
-    .AcqDelay           ( ClkPeriodSys * TTest )
-  ) i_dram_sim_mem (
-    .clk_i              ( clk   ),
-    .rst_ni             ( rst_n ),
-    .axi_req_i          ( axi_llc_mst_req ),
-    .axi_rsp_o          ( axi_llc_mst_rsp ),
-    .mon_w_valid_o      ( ),
-    .mon_w_addr_o       ( ),
-    .mon_w_data_o       ( ),
-    .mon_w_id_o         ( ),
-    .mon_w_user_o       ( ),
-    .mon_w_beat_count_o ( ),
-    .mon_w_last_o       ( ),
-    .mon_r_valid_o      ( ),
-    .mon_r_addr_o       ( ),
-    .mon_r_data_o       ( ),
-    .mon_r_id_o         ( ),
-    .mon_r_user_o       ( ),
-    .mon_r_beat_count_o ( ),
-    .mon_r_last_o       ( )
-  );
+  if (UseDramSys) begin : gen_dramsys
+    dram_sim_engine #(
+      .ClkPeriod  ( ClkPeriodSys )
+    ) i_dram_sim_engine (
+      .clk_i  ( clk   ),
+      .rst_ni ( rst_n )
+    );
+    axi_dram_sim #(
+      .AxiAddrWidth ( DutCfg.AddrWidth ),
+      .AxiDataWidth ( DutCfg.AxiDataWidth ),
+      .AxiIdWidth   ( $bits(axi_llc_id_t) ),
+      .AxiUserWidth ( DutCfg.AxiUserWidth ),
+      .BASE         ( DutCfg.LlcOutRegionStart ),
+      .DRAMType     ( "DDR4" ),
+      .CustomerDRAM ( "none" ),
+      .axi_req_t    ( axi_llc_req_t ),
+      .axi_resp_t   ( axi_llc_rsp_t ),
+      .axi_ar_t     ( axi_llc_ar_chan_t ),
+      .axi_r_t      ( axi_llc_r_chan_t ),
+      .axi_aw_t     ( axi_llc_aw_chan_t ),
+      .axi_w_t      ( axi_llc_w_chan_t ),
+      .axi_b_t      ( axi_llc_b_chan_t )
+    ) i_axi_dram_sim (
+      .clk_i      ( clk ),
+      .rst_ni     ( rst_n ),
+      .axi_req_i  ( axi_llc_mst_req ),
+      .axi_resp_o ( axi_llc_mst_rsp )
+    );
+  end else begin : gen_no_dramsys
+    axi_sim_mem #(
+      .AddrWidth          ( DutCfg.AddrWidth    ),
+      .DataWidth          ( DutCfg.AxiDataWidth ),
+      .IdWidth            ( $bits(axi_llc_id_t) ),
+      .UserWidth          ( DutCfg.AxiUserWidth ),
+      .axi_req_t          ( axi_llc_req_t ),
+      .axi_rsp_t          ( axi_llc_rsp_t ),
+      .WarnUninitialized  ( 0 ),
+      .ClearErrOnAccess   ( 1 ),
+      .ApplDelay          ( ClkPeriodSys * TAppl ),
+      .AcqDelay           ( ClkPeriodSys * TTest )
+    ) i_dram_sim_mem (
+      .clk_i              ( clk   ),
+      .rst_ni             ( rst_n ),
+      .axi_req_i          ( axi_llc_mst_req ),
+      .axi_rsp_o          ( axi_llc_mst_rsp ),
+      .mon_w_valid_o      ( ),
+      .mon_w_addr_o       ( ),
+      .mon_w_data_o       ( ),
+      .mon_w_id_o         ( ),
+      .mon_w_user_o       ( ),
+      .mon_w_beat_count_o ( ),
+      .mon_w_last_o       ( ),
+      .mon_r_valid_o      ( ),
+      .mon_r_addr_o       ( ),
+      .mon_r_data_o       ( ),
+      .mon_r_id_o         ( ),
+      .mon_r_user_o       ( ),
+      .mon_r_beat_count_o ( ),
+      .mon_r_last_o       ( )
+    );
+  end
 
   ///////////////////////////////
   //  SoC Clock, Reset, Modes  //

diff --git a/target/sim/vsim/start.cheshire_soc.tcl b/target/sim/vsim/start.cheshire_soc.tcl
@@ -9,13 +9,25 @@
 
 set TESTBENCH tb_cheshire_soc
 
+# Set full path to c++ compiler.
+if { ![info exists CXX_PATH] } {
+    if { ![info exists CXX] } {
+        if { ![info exists ::env(CXX)] } {
+            set CXX "g++"
+        } else {
+            set CXX $::env(CXX)
+        }
+    }
+    set CXX_PATH [exec which $CXX]
+}
+
 # Set voptargs only if not already set to make overridable.
 # Default on fast simulation flags.
 if { ![info exists VOPTARGS] } {
     set VOPTARGS "-O5 +acc=p+tb_cheshire_soc. +noacc=p+cheshire_soc. +acc=r+stream_xbar"
 }
 
-set flags "-permissive -suppress 3009 -suppress 8386 -error 7 "
+set flags "-permissive -suppress 3009 -suppress 8386 -error 7 -cpppath ${CXX_PATH} "
 if { [info exists SELCFG] } { append flags "-GSelectedCfg=${SELCFG} " }
 
 set pargs ""
@@ -24,6 +36,18 @@ if { [info exists PRELMODE] } { append pargs "+PRELMODE=${PRELMODE} " }
 if { [info exists BINARY] } { append pargs "+BINARY=${BINARY} " }
 if { [info exists IMAGE] } { append pargs "+IMAGE=${IMAGE} " }
 
+# DRAMSys
+if { [info exists USE_DRAMSYS] } {
+    append flags "-GUseDramSys=${USE_DRAMSYS} "
+    if { ${USE_DRAMSYS} } {
+        set DRAMSYS_ROOT "../dramsys"
+        set DRAMSYS_LIB "${DRAMSYS_ROOT}/build/lib"
+        append flags "-sv_lib ${DRAMSYS_LIB}/libsystemc "
+        append flags "-sv_lib ${DRAMSYS_LIB}/libDRAMSys_Simulator "
+        append pargs "+DRAMSYS_RES=${DRAMSYS_ROOT}/configs "
+    }
+}
+
 # tclint-disable-next-line command-args
 eval "vsim -c ${TESTBENCH} -t 1ps -vopt -voptargs=\"${VOPTARGS}\"" ${pargs} ${flags}