target/xilinx: Clean up flow, multi-board support, add VCU128 (#105)

* hw: Add `RegAdaptMemCut` inside `axi_to_reg_v2` * Bender.yml: Update `register_interface` * target/xilinx: Clean up flow, multi-board support, add VCU128 * sw: Update CVA6 SDK, add multi-device-tree flow * doc: Add new Xilinx target features * target/xilinx: Make utility targets weekly depend on input files * util: Add HS2 OpenOCD script, amend docs * doc: Some cleanup * nonfree: Update * doc: Fix typo --------- Co-authored-by: Cyril Koenig <[email protected]>
pulp-platform · Mar 6, 2024 · 3dca6cf · 3dca6cf
1 parent f316617
commit 3dca6cf
Show file tree

Hide file tree

Showing 44 changed files with 1,685 additions and 1,693 deletions.
diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
@@ -13,7 +13,7 @@ jobs:
   build:
     strategy:
       matrix:
-        target: [sw, hw, sim, xilinx]
+        target: [sw, hw, sim]
       fail-fast: false
     runs-on: ubuntu-22.04
     steps:

diff --git a/.gitignore b/.gitignore
@@ -23,6 +23,7 @@ site/
 *.gpth
 *.o
 *.a
+*.dtb
 sw/deps/.patched
 
 # Test models
@@ -35,3 +36,9 @@ target/sim/vsim/modelsim.ini
 target/sim/vsim/transcript
 target/sim/vsim/vsim.wlf
 target/sim/vsim/work/
+
+# Xilinx generated files
+target/xilinx/build
+target/xilinx/out
+target/xilinx/scripts/add_sources.*
+vivado*
diff --git a/Bender.lock b/Bender.lock
@@ -145,8 +145,8 @@ packages:
     - register_interface
     - tech_cells_generic
   register_interface:
-    revision: d7693be4aef1fc7e7eb2b00b41c42e87d959866c
-    version: 0.4.2
+    revision: e25b36670ff7aab3402f40efcc2b11ee0f31cf19
+    version: 0.4.3
     source:
       Git: https://github.com/pulp-platform/register_interface.git
     dependencies:

diff --git a/Bender.yml b/Bender.yml
@@ -26,7 +26,7 @@ dependencies:
   iDMA:                     { git: "https://github.com/pulp-platform/iDMA.git",                   version: 0.5.1  }
   irq_router:               { git: "https://github.com/pulp-platform/irq_router.git",             version: 0.0.1-beta.1 }
   opentitan_peripherals:    { git: "https://github.com/pulp-platform/opentitan_peripherals.git",  version: 0.4.0  }
-  register_interface:       { git: "https://github.com/pulp-platform/register_interface.git",     version: 0.4.2  }
+  register_interface:       { git: "https://github.com/pulp-platform/register_interface.git",     version: 0.4.3  }
   riscv-dbg:                { git: "https://github.com/pulp-platform/riscv-dbg.git",              version: 0.8.0  }
   serial_link:              { git: "https://github.com/pulp-platform/serial_link.git",            version: 1.1.0  }
   unbent:                   { git: "https://github.com/pulp-platform/unbent.git",                 version: 0.1.6  }
@@ -52,5 +52,7 @@ sources:
 
   - target: all(fpga, xilinx)
     files:
+      - target/xilinx/src/phy_definitions.svh
+      - target/xilinx/src/dram_wrapper_xilinx.sv
       - target/xilinx/src/fan_ctrl.sv
       - target/xilinx/src/cheshire_top_xilinx.sv
diff --git a/cheshire.mk b/cheshire.mk
@@ -53,7 +53,7 @@ chs-clean-deps:
 ######################
 
 CHS_NONFREE_REMOTE ?= [email protected]:pulp-restricted/cheshire-nonfree.git
-CHS_NONFREE_COMMIT ?= dafd3c1
+CHS_NONFREE_COMMIT ?= 99973e8
 
 chs-nonfree-init:
 	git clone $(CHS_NONFREE_REMOTE) $(CHS_ROOT)/nonfree
@@ -159,18 +159,15 @@ CHS_SIM_ALL += $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl
 # FPGA Flow #
 #############
 
-$(CHS_ROOT)/target/xilinx/scripts/add_sources.tcl: $(CHS_ROOT)/Bender.yml
-	$(BENDER) script vivado -t fpga -t cv64a6_imafdcsclic_sv39 -t cva6 > $@
-
-CHS_XILINX_ALL += $(CHS_ROOT)/target/xilinx/scripts/add_sources.tcl
+include target/xilinx/xilinx.mk
 
 #################################
 # Phonies (KEEP AT END OF FILE) #
 #################################
 
 .PHONY: chs-all chs-nonfree-init chs-clean-deps chs-sw-all chs-hw-all chs-bootrom-all chs-sim-all chs-xilinx-all
 
-CHS_ALL += $(CHS_SW_ALL) $(CHS_HW_ALL) $(CHS_SIM_ALL) $(CHS_XILINX_ALL)
+CHS_ALL += $(CHS_SW_ALL) $(CHS_HW_ALL) $(CHS_SIM_ALL)
 
 chs-all:         $(CHS_ALL)
 chs-sw-all:      $(CHS_SW_ALL)

diff --git a/docs/tg/xilinx.md b/docs/tg/xilinx.md
@@ -7,23 +7,23 @@ This page describes how to map Cheshire on Xilinx FPGAs to *execute baremetal pr
 We currently provide working setups for:
 
 - Digilent Genesys 2 with Vivado `>= 2020.2`
+- Xilinx VCU128 with Vivado `>= 2020.2`
 
 We are working on support for more boards in the future.
 
 ## Implementation
 
-Since the implementation steps and available features vary between boards, we provide instructions and document available features for each.
-
-### Digilent Genesys 2
-
-Generate the bitstream `target/xilinx/out/cheshire_top_xilinx.bit` by running:
+Generate the bitstream `target/xilinx/out/cheshire.<myboard>.bit` for your desired board by running:
 
 ```
-make -C target/xilinx
+make chs-xilinx-<myboard>
 ```
 
-Before flashing the bitstream to your device, take note of the position of onboard switches, which control important functionality:
+Since available features vary between boards, we provide further documentation for each.
 
+### Digilent Genesys 2 (`genesys2`)
+
+Before flashing the bitstream to your device, take note of the position of onboard switches, which control important functionality:
 
   | Switch | Function                                        |
   | ------ | ------------------------------------------------|
@@ -33,14 +33,41 @@ Before flashing the bitstream to your device, take note of the position of onboa
 
 The reset, JTAG TAP, UART, I2C, and VGA are all connected to their onboard logic or ports. The UART has *no flow control*. The microSD slot is connected to chip select 0 of the SPI host peripheral. Serial link and GPIOs are currently not available.
 
+### Xilinx VCU128 (`vcu128`)
+
+Since there are no switches on this board, the boot mode must be selected using Virtual IOs (see [Virtual IOs](#virtual_ios) below).
+
+This board provides a JTAG TAP and a UART without flow control connected to onboard ports. The SPI host peripheral connects to the `STARTUPE3` IP block, which provides access to the onboard flash. All other IOs are currently not available.
+
+### Virtual IOs
+
+To provide control of important IO without direct access to onboard switches, we provide the following virtual IOs on all boards, which may be controlled at runtime through Vivado's hardware manager:
+
+  | Virtual IO          | Function                                   |
+  | ------------------- | -------------------------------------------|
+  | `vio_reset`         | Assert reset (active high)                 |
+  | `vio_boot_mode`     | Externally override boot mode              |
+  | `vio_boot_mode_sel` | Whether to override boot mode from FPGA IO |
+
+### Inserting ILA probes
+
+For analysis and debugging purposes, integrated logic analyzer (ILA) probes may be added to the design's RTL description. You can do this either by marking signals with appropriate attributes or by using the `ila` macro from the `phy_definitions.svh` header:
+
+```systemverilog
+/* Option 1 */ (* dont_touch = "yes" *) (* mark_debug = "true" *) logic mysignal;
+/* Option 2 */ `ila(my_ila_name, mysignal)
+```
+
 ## Debugging with OpenOCD
 
 To establish a debug bridge over JTAG, ensure the target is in a debuggable state (for example by resetting into the idle boot mode 0) and launch OpenOCD with:
 
 ```
-openocd -f $(bender path ariane)/corev_apu/fpga/ariane.cfg
+openocd -f util/openocd.<board_or_adapter>.tcl
 ```
 
+If multiple JTAG adapters are connected to your debugging machine, you may have to extend the script to specify desired adapter's serial number.
+
 In another shell, launch a RISC-V GDB session attaching to OpenOCD:
 
 ```
@@ -55,7 +82,7 @@ You can now interrupt (Ctrl+C), inspect, and repoint execution with GDB as usual
 
 ## Running Baremetal Code
 
-Baremetal code can be preloaded through JTAG using OpenOCD and GDB or loaded from an SD Card. In principle, other interfaces may also be used to boot if the board provides them, but no setups are available for this.
+Baremetal code can be preloaded through JTAG using OpenOCD and GDB or loaded from a bootable device, such as an SD card. In principle, other interfaces may also be used to boot if the board provides them, but no setups are available for this.
 
 First, connect to UART using a serial communication program like minicom:
 
@@ -78,9 +105,9 @@ continue
 
 You should see `Hello World!` output printed on the UART.
 
-### Boot from SD Card
+### Boot from SD card (`genesys2` only)
 
-First, build an up-to-date a disk image for your desired binary. For `helloworld`:
+First, build an up-to-date GPT disk image for your desired binary. For `helloworld`:
 
 ```
 make sw/tests/helloworld.gpt.bin
@@ -97,6 +124,20 @@ The second command only ensures correctness of the partition layout; it moves th
 
 Insert your SD card and reset into boot mode 1. You should see a `Hello World!` UART output.
 
+### Boot from onboard flash (`vcu128` only)
+
+Build a GPT disk image for your desired binary as explained above, then flash it to your board's flash. For `helloworld`:
+
+```
+make CHS_XILINX_FLASH_BIN=sw/tests/helloworld.gpt.bin chs-xilinx-flash-<myboard>
+```
+
+Flashing an image should take about 10 minutes. *Note that after flashing, your board's bitstream must be reprogrammed* as it is overridden for this task.
+
+If the image given by `CHS_XILINX_FLASH_BIN` does not exist, `make` will attempt to build it before flashing. If `CHS_XILINX_FLASH_BIN` is not provided, the target assumes the board's Linux image by default.
+
+After flashing your disk image and reprogramming your bitstream, reset into boot mode 2. For `helloworld`, you should again see a `Hello World!` UART output.
+
 ## Booting Linux
 
 To boot Linux, we must load the *OpenSBI* firmware, which takes over M mode and launches the U-boot bootloader. U-boot then loads Linux. For more details, see [Boot Flow](../um/sw.md#boot-flow).
@@ -108,17 +149,17 @@ git submodule update --init --recursive sw/deps/cva6-sdk
 cd sw/deps/cva6-sdk && make images
 ```
 
-In principle, we can boot Linux through JTAG by loading all images into memory, launching OpenSBI, and instructing U-boot to load the kernel directly from memory. Here, we focus on autonomous boot from SD card.
+In principle, we can boot Linux through JTAG by loading all images into memory, launching OpenSBI, and instructing U-boot to load the kernel directly from memory. Here, we focus on autonomous boot from SD card or SPI flash.
 
 In this case, OpenSBI is loaded by a regular baremetal program called the [Zero-Stage Loader](../um/sw.md#zero-stage-loader) (ZSL). The [boot ROM](../um/sw.md#boot-rom) loads the ZSL from SD card, which then loads the device tree and firmware from other SD card partitions into memory and launches OpenSBI.
 
-To create a full Linux disk image from the ZSL, device tree, firmware, and Linux, run:
+To create a full Linux disk image from the ZSL, your board's device tree, the firmware, and Linux, run:
 
 ```
-make ${CHS_ROOT}/sw/boot/linux.gpt.bin
+make ${CHS_ROOT}/sw/boot/linux.<myboard>.gpt.bin
 ```
 
-where `CHS_ROOT` is the root of the Cheshire repository. Flash this image to an SD card as you did in the previous section, then insert the SD card and reset into boot mode 1. You should first see the ZSL print on the UART:
+where `CHS_ROOT` is the root of the Cheshire repository. Flash this image to an SD card or SPI flash as described in the preceding sections, then reset into the boot mode corresponding for your boot medium. You should first see the ZSL print on the UART:
 
 ```
  /\___/\       Boot mode:       1

diff --git a/docs/um/arch.md b/docs/um/arch.md
@@ -151,6 +151,7 @@ The internal interconnect exposes the following parameters:
 | `RegMax(Read|Write)Txns`    | `dw_bt`      | Max. inflight transactions at Regbus AMO filter   |
 | `RegAmoNumCuts`             | `aw_bt`      | Number of timing cuts inside Regbus AMO filter    |
 | `RegAmoPostCut`             | `bit`        | Whether to insert a cut after Regbus AMO filter   |
+| `RegAdaptMemCut`            | `bit`        | Whether to insert a cut inside AXI-to-Rb. adapter |
 | `(Axi|Reg)ExtNum(Mst|Slv)`  | `0..15`      | AXI4 and Regbus number of external Mgrs. or Subs. |
 | `(Axi|Reg)ExtNumRules`      | `0..15`      | AXI4 and Regbus number of external address rules  |
 | `(Axi|Reg)ExtRegion*`       | `doub_bt`    | AXI4 and Regbus external address regions          |

diff --git a/hw/cheshire_pkg.sv b/hw/cheshire_pkg.sv
@@ -105,6 +105,7 @@ package cheshire_pkg;
     dw_bt   RegMaxWriteTxns;
     aw_bt   RegAmoNumCuts;
     bit     RegAmoPostCut;
+    bit     RegAdaptMemCut;
     // External AXI ports (limited number of ports and rules)
     bit     [MaxExtAxiMstWidth-1:0]     AxiExtNumMst;
     bit     [MaxExtAxiSlvWidth-1:0]     AxiExtNumSlv;
@@ -579,6 +580,7 @@ package cheshire_pkg;
     RegMaxWriteTxns   : 8,
     RegAmoNumCuts     : 1,
     RegAmoPostCut     : 1,
+    RegAdaptMemCut    : 1,
     // RTC
     RtcFreq           : 32768,
     // Features

diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv
@@ -361,7 +361,8 @@ module cheshire_soc import cheshire_pkg::*; #(
     .AxiDataWidth ( Cfg.AxiDataWidth ),
     .AxiIdWidth   ( AxiSlvIdWidth    ),
     .AxiUserWidth ( Cfg.AxiUserWidth ),
-    .RegDataWidth ( 32'd32 ),
+    .RegDataWidth ( 32 ),
+    .CutMemReqs   ( Cfg.RegAdaptMemCut ),
     .axi_req_t    ( axi_slv_req_t ),
     .axi_rsp_t    ( axi_slv_rsp_t ),
     .reg_req_t    ( reg_req_t ),

diff --git a/sw/boot/cheshire.dts → sw/boot/cheshire.dtsi b/sw/boot/cheshire.dts → sw/boot/cheshire.dtsi
@@ -7,11 +7,13 @@
 // Axel Vanoni <[email protected]>
 
 /dts-v1/;
+
 / {
   #address-cells = <2>;
   #size-cells = <2>;
   compatible = "eth,cheshire-dev";
   model = "eth,cheshire";
+
   chosen {
     stdout-path = "/soc/serial@3002000:115200";
   };
@@ -74,22 +76,16 @@
       interrupts = <2 3 4 5 6 7 8 9 10 11 12 13 14 15 16>;
       reg = <0x0 0x3003000 0x0 0x1000>;
     };
-    spi@3004000 {
+    spi: spi@3004000 {
       compatible = "opentitan,spi-host", "lowrisc,spi";
       interrupt-parent = <&PLIC0>;
       interrupts = <17 18>;
       reg = <0x0 0x3004000 0x0 0x1000>;
+      num-cs = <2>;
       clock-frequency = <50000000>;
       max-frequency = <25000000>;
       #address-cells = <1>;
       #size-cells = <0>;
-      mmc@0 {
-        compatible = "mmc-spi-slot";
-        reg = <0>;
-        spi-max-frequency = <25000000>;
-        voltage-ranges = <3300 3300>;
-        disable-wp;
-      };
     };
     vga@3007000 {
       compatible = "eth,axi-vga";

diff --git a/sw/boot/cheshire.genesys2.dts b/sw/boot/cheshire.genesys2.dts
@@ -0,0 +1,18 @@
+// Copyright 2024 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Cyril Koenig <[email protected]>
+
+/include/ "cheshire.dtsi"
+
+&spi {
+  boot-with = <0>;
+  mmc@0 {
+    compatible = "mmc-spi-slot";
+    reg = <0>; // CS
+    spi-max-frequency = <25000000>;
+    voltage-ranges = <3300 3300>;
+    disable-wp;
+  };
+};
diff --git a/sw/boot/cheshire.vcu128.dts b/sw/boot/cheshire.vcu128.dts
@@ -0,0 +1,27 @@
+// Copyright 2024 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Cyril Koenig <[email protected]>
+
+/include/ "cheshire.dtsi"
+
+&spi {
+  boot-with = <1>;
+  nor@1 {
+    #address-cells = <0x1>;
+    #size-cells = <0x1>;
+    // Note : u-boot does not find mt25qu02g
+    compatible = "mt25qu02g", "jedec,spi-nor";
+    reg = <0x1>; // CS
+    spi-max-frequency = <25000000>;
+    spi-rx-bus-width = <0x1>;
+    spi-tx-bus-width = <0x1>;
+    disable-wp;
+    partition@0 {
+      label = "all";
+      reg = <0x0 0x6000000>; // 96 MB
+      read-only;
+    };
+  };
+};
diff --git a/sw/deps/cva6-sdk b/sw/deps/cva6-sdk
diff --git a/sw/sw.mk b/sw/sw.mk
@@ -140,7 +140,7 @@ $(foreach link,$(patsubst $(CHS_SW_LD_DIR)/%.ld,%,$(wildcard $(CHS_SW_LD_DIR)/*.
 CHS_CVA6_SDK_IMGS ?= $(addprefix $(CHS_SW_DIR)/deps/cva6-sdk/install64/,fw_payload.bin uImage)
 
 # Create full Linux disk image
-$(CHS_SW_DIR)/boot/linux.gpt.bin: $(CHS_SW_DIR)/boot/zsl.rom.bin $(CHS_SW_DIR)/boot/cheshire.dtb $(CHS_CVA6_SDK_IMGS)
+$(CHS_SW_DIR)/boot/linux.%.gpt.bin: $(CHS_SW_DIR)/boot/zsl.rom.bin $(CHS_SW_DIR)/boot/cheshire.%.dtb $(CHS_CVA6_SDK_IMGS)
 	truncate -s $(CHS_SW_DISK_SIZE) $@
 	sgdisk --clear -g --set-alignment=1 \
 		--new=1:64:96 --typecode=1:$(CHS_SW_ZSL_TGUID) \

diff --git a/target/xilinx/.gitignore b/target/xilinx/.gitignore
+2 −2		Makefile
+1 −1		opensbi
+1 −0		rootfs/etc/profile.d/helloworld.sh
+1 −1		u-boot