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treewide: Update CVA6 to pulp-v2
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@paulsc96
paulsc96 committed Nov 6, 2024
1 parent 0b3e364 commit 2618141
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Showing 6 changed files with 44 additions and 72 deletions.
6 changes: 3 additions & 3 deletions Bender.lock
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Expand Up @@ -92,7 +92,7 @@ packages:
Git: https://github.com/pulp-platform/common_verification.git
dependencies: []
cva6:
revision: 9338c2ca7cf1a47aef54322f89ce867825c3c8d5
revision: fd43252aa6745d0746ae0367ccf24ad9522f2ae1
version: null
source:
Git: https://github.com/pulp-platform/cva6.git
Expand All @@ -109,8 +109,8 @@ packages:
dependencies:
- axi
fpnew:
revision: f231041c610f270ffc03cbdac38739ddb6426572
version: null
revision: e5aa6a01b5bbe1675c3aa8872e1203413ded83d1
version: 0.2.3
source:
Git: https://github.com/pulp-platform/cvfpu.git
dependencies:
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2 changes: 1 addition & 1 deletion Bender.yml
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Expand Up @@ -22,7 +22,7 @@ dependencies:
clint: { git: "https://github.com/pulp-platform/clint.git", version: 0.2.0 }
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.33.0 }
common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.0 }
cva6: { git: "https://github.com/pulp-platform/cva6.git", rev: pulp-v1.0.0 }
cva6: { git: "https://github.com/pulp-platform/cva6.git", rev: paulsc/v2r-chs }
iDMA: { git: "https://github.com/pulp-platform/iDMA.git", version: 0.5.1 }
irq_router: { git: "https://github.com/pulp-platform/irq_router.git", version: 0.0.1-beta.1 }
opentitan_peripherals: { git: "https://github.com/pulp-platform/opentitan_peripherals.git", version: 0.4.0 }
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5 changes: 4 additions & 1 deletion cheshire.mk
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Expand Up @@ -13,6 +13,9 @@ CXX_PATH := $(shell which $(CXX))

VLOG_ARGS ?= -suppress 2583 -suppress 13314 -timescale 1ns/1ps

# Bender flags for CVA6; specify configuration target here.
CHS_CVA6_BENDER_FLAGS ?= -t cv64a6_imafdc_sv39_hpdcache -t cva6

# Define used paths (prefixed to avoid name conflicts)
CHS_ROOT ?= $(shell $(BENDER) path cheshire)
CHS_REG_DIR := $(shell $(BENDER) path register_interface)
Expand Down Expand Up @@ -139,7 +142,7 @@ CHS_BOOTROM_ALL += $(CHS_ROOT)/hw/bootrom/cheshire_bootrom.sv $(CHS_ROOT)/hw/boo
##############

$(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl: $(CHS_ROOT)/Bender.yml
$(BENDER) script vsim -t sim -t cv64a6_imafdcsclic_sv39 -t test -t cva6 -t rtl --vlog-arg="$(VLOG_ARGS)" > $@
$(BENDER) script vsim $(CHS_CVA6_BENDER_FLAGS) -t sim -t test -t rtl --vlog-arg="$(VLOG_ARGS)" > $@
echo 'vlog "$(realpath $(CHS_ROOT))/target/sim/src/elfloader.cpp" -ccflags "-std=c++11" -cpppath "$(CXX_PATH)"' >> $@

.PRECIOUS: $(CHS_ROOT)/target/sim/models
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97 changes: 33 additions & 64 deletions hw/cheshire_pkg.sv
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Expand Up @@ -480,74 +480,43 @@ package cheshire_pkg;
endcase
endfunction

function automatic config_pkg::cva6_cfg_t gen_cva6_cfg(cheshire_cfg_t cfg);
function automatic config_pkg::cva6_user_cfg_t gen_cva6_cfg(cheshire_cfg_t cfg);
doub_bt SizeSpm = get_llc_size(cfg);
doub_bt SizeLlcOut = cfg.LlcOutRegionEnd - cfg.LlcOutRegionStart;
doub_bt CieBase = cfg.Cva6ExtCieOnTop ? 64'h8000_0000 - cfg.Cva6ExtCieLength : 64'h2000_0000;
doub_bt NoCieBase = cfg.Cva6ExtCieOnTop ? 64'h2000_0000 : 64'h2000_0000 + cfg.Cva6ExtCieLength;
return config_pkg::cva6_cfg_t'{
NrCommitPorts : 2,
AxiAddrWidth : cfg.AddrWidth,
AxiDataWidth : cfg.AxiDataWidth,
AxiIdWidth : Cva6IdWidth,
AxiUserWidth : cfg.AxiUserWidth,
NrLoadBufEntries : 2,
FpuEn : 1,
XF16 : 0,
XF16ALT : 0,
XF8 : 0,
XF8ALT : 0,
RVA : 1,
RVB : 0,
RVV : 0,
RVC : 1,
RVH : 1,
RVZCB : 1,
XFVec : 0,
CvxifEn : 0,
ZiCondExtEn : 1,
RVSCLIC : cfg.Clic,
RVF : 1,
RVD : 1,
FpPresent : 1,
NSX : 0,
FLen : 64,
RVFVec : 0,
XF16Vec : 0,
XF16ALTVec : 0,
XF8Vec : 0,
NrRgprPorts : 0,
NrWbPorts : 0,
EnableAccelerator : 0,
RVS : 1,
RVU : 1,
HaltAddress : AmDbg + 'h800,
ExceptionAddress : AmDbg + 'h808,
RASDepth : cfg.Cva6RASDepth,
BTBEntries : cfg.Cva6BTBEntries,
BHTEntries : cfg.Cva6BHTEntries,
DmBaseAddress : AmDbg,
TvalEn : 1,
NrPMPEntries : cfg.Cva6NrPMPEntries,
PMPCfgRstVal : {16{64'h0}},
PMPAddrRstVal : {16{64'h0}},
PMPEntryReadOnly : 16'd0,
NOCType : config_pkg::NOC_TYPE_AXI4_ATOP,
CLICNumInterruptSrc : NumCoreIrqs + NumIntIntrs + cfg.NumExtClicIntrs,
NrNonIdempotentRules : 2, // Periphs, ExtNonCIE
NonIdempotentAddrBase : {64'h0000_0000, NoCieBase},
NonIdempotentLength : {64'h1000_0000, 64'h6000_0000 - cfg.Cva6ExtCieLength},
NrExecuteRegionRules : 5, // Debug, Bootrom, AllSPM, LLCOut, ExtCIE
ExecuteRegionAddrBase : {AmDbg, AmBrom, AmSpm, cfg.LlcOutRegionStart, CieBase},
ExecuteRegionLength : {64'h40000, 64'h40000, 2*SizeSpm, SizeLlcOut, cfg.Cva6ExtCieLength},
NrCachedRegionRules : 3, // CachedSPM, LLCOut, ExtCIE
CachedRegionAddrBase : {AmSpm, cfg.LlcOutRegionStart, CieBase},
CachedRegionLength : {SizeSpm, SizeLlcOut, cfg.Cva6ExtCieLength},
MaxOutstandingStores : 7,
DebugEn : 1,
NonIdemPotenceEn : 0,
AxiBurstWriteEn : 0
};
// Base our config on the upstream default for this variant
config_pkg::cva6_user_cfg_t ret = cva6_config_pkg::cva6_cfg;
// Modify what we need to
ret.AxiAddrWidth = cfg.AddrWidth;
ret.AxiDataWidth = cfg.AxiDataWidth;
ret.AxiIdWidth = Cva6IdWidth;
ret.AxiUserWidth = cfg.AxiUserWidth;
ret.DmBaseAddress = AmDbg;
ret.HaltAddress = AmDbg + 'h800;
ret.ExceptionAddress = AmDbg + 'h808;
ret.NrNonIdempotentRules = 2; // Periphs, ExtNonCI;
ret.NonIdempotentAddrBase = {64'h0000_0000, NoCieBase};
ret.NOCType = config_pkg::NOC_TYPE_AXI4_ATOP;
ret.NonIdempotentLength = {64'h1000_0000, 64'h6000_0000 - cfg.Cva6ExtCieLength};
ret.NrExecuteRegionRules = 5; // Debug, Bootrom, AllSPM, LLCOut, ExtCI;
ret.ExecuteRegionAddrBase = {AmDbg, AmBrom, AmSpm, cfg.LlcOutRegionStart, CieBase};
ret.ExecuteRegionLength = {64'h40000, 64'h40000, 2*SizeSpm, SizeLlcOut, cfg.Cva6ExtCieLength};
ret.NrCachedRegionRules = 3; // CachedSPM, LLCOut, ExtCI;
ret.CachedRegionAddrBase = {AmSpm, cfg.LlcOutRegionStart, CieBase};
ret.CachedRegionLength = {SizeSpm, SizeLlcOut, cfg.Cva6ExtCieLength};
ret.DebugEn = 1;
ret.RVSCLIC = cfg.Clic;
ret.CLICNumInterruptSrc = NumCoreIrqs + NumIntIntrs + cfg.NumExtClicIntrs;
// TODO: Should some things be removed from the main config?
// TODO: Should other things be added to the main config?
// TODO: Tune missing parameters of interest (esp. cache and interconnect) properly
ret.RASDepth = cfg.Cva6RASDepth;
ret.BTBEntries = cfg.Cva6BTBEntries;
ret.BHTEntries = cfg.Cva6BHTEntries;
ret.NrPMPEntries = cfg.Cva6NrPMPEntries;
// Return modified config
return ret;
endfunction

////////////////
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4 changes: 2 additions & 2 deletions hw/cheshire_soc.sv
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Expand Up @@ -558,7 +558,7 @@ module cheshire_soc import cheshire_pkg::*; #(

`CHESHIRE_TYPEDEF_AXI_CT(axi_cva6, addr_t, cva6_id_t, axi_data_t, axi_strb_t, axi_user_t)

localparam config_pkg::cva6_cfg_t Cva6Cfg = gen_cva6_cfg(Cfg);
localparam config_pkg::cva6_user_cfg_t Cva6Cfg = gen_cva6_cfg(Cfg);

// Boot from boot ROM only if available, otherwise from platform ROM
localparam logic [63:0] BootAddr = 64'(Cfg.Bootrom ? AmBrom : Cfg.PlatformRom);
Expand Down Expand Up @@ -600,7 +600,7 @@ module cheshire_soc import cheshire_pkg::*; #(
riscv::priv_lvl_t clic_irq_priv;

cva6 #(
.CVA6Cfg ( Cva6Cfg ),
.CVA6Cfg ( build_config_pkg::build_config(Cva6Cfg) ),
.axi_ar_chan_t ( axi_cva6_ar_chan_t ),
.axi_aw_chan_t ( axi_cva6_aw_chan_t ),
.axi_w_chan_t ( axi_cva6_w_chan_t ),
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2 changes: 1 addition & 1 deletion target/xilinx/xilinx.mk
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Expand Up @@ -41,7 +41,7 @@ CHS_XILINX_IPS_genesys2 := clkwiz vio mig7s
CHS_XILINX_IPS_vcu128 := clkwiz vio ddr4

$(CHS_XILINX_DIR)/scripts/add_sources.%.tcl: $(CHS_ROOT)/Bender.yml
$(BENDER) script vivado -t fpga -t cv64a6_imafdcsclic_sv39 -t cva6 -t $* > $@
$(BENDER) script vivado $(CHS_CVA6_BENDER_FLAGS) -t fpga -t $* > $@

define chs_xilinx_bit_rule
$$(CHS_XILINX_DIR)/out/%.$(1).bit: \
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