fpga: Testing ddr4

Bender.yml

@@ -47,7 +47,7 @@ sources:
       - target/sim/src/fixture_cheshire_soc.sv
       - target/sim/src/tb_cheshire_soc.sv
 
-  - target: all(fpga, xilinx)
+  - target: any(fpga, xilinx)
     files:
       - target/xilinx/src/fan_ctrl.sv
       - target/xilinx/src/dram_wrapper.sv

cheshire.mk

@@ -55,7 +55,7 @@ chs-clean-deps:
 ######################
 
 CHS_NONFREE_REMOTE ?= [email protected]:pulp-restricted/cheshire-nonfree.git
-CHS_NONFREE_COMMIT ?= e702b4ce754c3b7c9a864a2ce8e2d2fa013056ea
+CHS_NONFREE_COMMIT ?= b11f9e5fbc97209da75e77c93a1e4e0460dddf6c
 
 chs-nonfree-init:
 	git clone $(CHS_NONFREE_REMOTE) $(CHS_ROOT)/nonfree
@@ -158,3 +158,4 @@ chs-sim-all: $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl
 #############
 
 include $(CHS_ROOT)/target/xilinx/xilinx.mk
+include $(CHS_XIL_DIR)/sim/simulate.mk

target/xilinx/constraints/cheshire.xdc

@@ -13,21 +13,12 @@
 set_property DONT_TOUCH TRUE [get_cells i_sys_clk_div/i_clk_bypass_mux]
 
 # The net of which we get the 200 MHz single ended clock from the MIG
-set MIG_CLK_SRC [get_pins -filter {DIRECTION == OUT} -leaf -of_objects [get_nets dram_clock_out]]
-set MIG_RST_SRC [get_pins -filter {DIRECTION == OUT} -leaf -of_objects [get_nets dram_sync_reset]]
-
 set SOC_RST_SRC [get_pins -filter {DIRECTION == OUT} -leaf -of_objects [get_nets rst_n]]
 
 #####################
 # Timing Parameters #
 #####################
 
-# 333 MHz (max) DRAM Axi clock
-set FPGA_TCK 3.0
-
-# 200 MHz DRAM Generated clock
-set DRAM_TCK 5.0
-
 # 50 MHz SoC clock
 set SOC_TCK 20.0
 
@@ -44,25 +35,40 @@ set UART_IO_SPEED 200.0
 # Clocks #
 ##########
 
+# Clk_wiz clocks
+create_clock -period 100 -name clk_10 [get_pins i_xlnx_clk_wiz/clk_10]
+create_clock -period 50 -name clk_20 [get_pins i_xlnx_clk_wiz/clk_20]
+create_clock -period 20 -name clk_50 [get_pins i_xlnx_clk_wiz/clk_50]
+create_clock -period 10 -name clk_100 [get_pins i_xlnx_clk_wiz/clk_100]
+
 # System Clock
-create_generated_clock -name clk_soc -source $MIG_CLK_SRC -divide_by 4 [get_nets soc_clk]
+# [see in board.xdc]
+
 # JTAG Clock
 create_clock -period $JTAG_TCK -name clk_jtag [get_ports jtag_tck_i]
 set_input_jitter clk_jtag 1.000
 
+##########
+# BUFG   #
+##########
+
+# JTAG are on non clock capable GPIOs (if not using BSCANE)
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_ports jtag_tck_i]]
+set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_ports jtag_tck_i]]
+
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_ports cpu_reset]]
+set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_ports cpu_reset]]
+
+set all_in_mux [get_nets -of [ get_pins -filter { DIRECTION == IN } -of [get_cells -hier -filter { ORIG_REF_NAME == tc_clk_mux2 || REF_NAME == tc_clk_mux2 }]]]
+set_property CLOCK_DEDICATED_ROUTE FALSE $all_in_mux
+set_property CLOCK_BUFFER_TYPE NONE $all_in_mux
+
 ################
 # Clock Groups #
 ################
 
 # JTAG Clock is asynchronous to all other clocks
-set_clock_groups -name jtag_async -asynchronous -group [get_clocks clk_jtag]
-
-#######################
-# Placement Overrides #
-#######################
-
-# Accept suboptimal BUFG-BUFG cascades
-set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_sys_clk_div/i_clk_mux/clk0_i]
+set_clock_groups -name jtag_async -asynchronous -group {clk_jtag}
 
 ########
 # JTAG #
@@ -77,13 +83,6 @@ set_output_delay -max -clock clk_jtag [expr 0.20 * $JTAG_TCK] [get_ports jtag_td
 set_max_delay  -from [get_ports jtag_trst_ni] $JTAG_TCK
 set_false_path -hold -from [get_ports jtag_trst_ni]
 
-#######
-# MIG #
-#######
-
-set_max_delay  -from $MIG_RST_SRC $FPGA_TCK
-set_false_path -hold -from $MIG_RST_SRC
-
 ########
 # UART #
 ########
@@ -101,15 +100,6 @@ set_false_path -hold -to [get_ports uart_tx_o]
 # cdc_fifo_gray: Disable hold checks, limit datapath delay and bus skew
 set_property KEEP_HIERARCHY SOFT [get_cells i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*i_sync]
 set_false_path -hold -through [get_pins -of_objects [get_cells i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*]] -through [get_pins -of_objects [get_cells i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*]]
-set_max_delay -datapath -from [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_dst_*/*i_sync/reg*/D] $FPGA_TCK
-set_max_delay -datapath -from [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_src_*/*i_sync/reg*/D] $FPGA_TCK
-set_max_delay -datapath -from [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] $FPGA_TCK
-
-###################
-# Reset Generator #
-###################
-
-set_max_delay -from $SOC_RST_SRC $SOC_TCK
-set_false_path -hold -from $SOC_RST_SRC
 
-set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets i_xlnx_clk_wiz/inst/clkin1_ibufds/O]
+set_false_path -hold -through [get_pins -of_objects [get_cells -hier -filter {ORIG_REF_NAME == axi_cdc_src || REF_NAME == axi_cdc_src}] -filter {NAME =~ *async*}]
+set_false_path -hold -through [get_pins -of_objects [get_cells -hier -filter {ORIG_REF_NAME == axi_cdc_dst || REF_NAME == axi_cdc_dst}] -filter {NAME =~ *async*}]

target/xilinx/constraints/genesys2.xdc

@@ -5,6 +5,29 @@
 # Testmode is set to 0 during normal use
 set_case_analysis 0 [get_ports testmode_i]
 
+
+set all_in_mux [get_nets -of [ get_pins -filter { DIRECTION == IN } -of [get_cells -hier -filter { ORIG_REF_NAME == tc_clk_mux2 || REF_NAME == tc_clk_mux2 }]]]
+set_property CLOCK_DEDICATED_ROUTE FALSE $all_in_mux
+set_property CLOCK_BUFFER_TYPE NONE $all_in_mux
+
+#############
+# Sys clock #
+#############
+
+create_clock -period 5 -name sys_clk [get_pins u_ibufg_sys_clk/O]
+set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins u_ibufg_sys_clk/O]
+set_clock_groups -name sys_clk_async -asynchronous -group {sys_clk}
+
+
+#############
+# Mig clock #
+#############
+
+set MIG_RST [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst]
+create_clock -period 5 -name dram_axi_clk [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk]
+set_false_path -hold -through $MIG_RST
+set_max_delay -through $MIG_RST 5 
+
 #######
 # VGA #
 #######
@@ -54,8 +77,8 @@ set_false_path -hold -to [get_ports {i2c_scl_io i2c_sda_io}]
 ###############
 
 ## Clock Signal
-# set_property -dict { PACKAGE_PIN AD11  IOSTANDARD LVDS     } [get_ports { sysclk_n }]; #IO_L12N_T1_MRCC_33 Sch=sysclk_n
-# set_property -dict { PACKAGE_PIN AD12  IOSTANDARD LVDS     } [get_ports { sysclk_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p
+set_property -dict { PACKAGE_PIN AD11  IOSTANDARD LVDS     } [get_ports { sys_clk_n }]; #IO_L12N_T1_MRCC_33 Sch=sysclk_n
+set_property -dict { PACKAGE_PIN AD12  IOSTANDARD LVDS     } [get_ports { sys_clk_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p
 
 ## Buttons
 #set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS12 } [get_ports { btnc }]; #IO_25_17 Sch=btnc

target/xilinx/constraints/vcu128.xdc

@@ -2,9 +2,27 @@
 # BOARD SPECIFIC CONSTRAINTS #
 ##############################
 
-# JTAG are on non clock capable GPIOs (if not using BSCANE)
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_ports jtag_tck_i]]
-set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_ports jtag_tck_i]]
+#############
+# Sys clock #
+#############
+
+create_clock -period 10 -name sys_clk [get_pins u_ibufg_sys_clk/O]
+set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins u_ibufg_sys_clk/O]
+set_clock_groups -name sys_clk_async -asynchronous -group {sys_clk}
+
+#############
+# Mig clock #
+#############
+
+set MIG_RST [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst]
+#create_clock -period 10 -name dram_axi_clk [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk]
+set_false_path -hold -through $MIG_RST
+set_max_delay -through $MIG_RST 10
+
+set_max_delay -datapath -from [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_dst_*/*i_sync/reg*/D] $FPGA_TCK
+set_max_delay -datapath -from [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] $FPGA_TCK
+
+
 
 #################################################################################
 

target/xilinx/constraints/zcu102.xdc

@@ -1,3 +1,31 @@
+##############################
+# BOARD SPECIFIC CONSTRAINTS #
+##############################
+
+#############
+# Sys clock #
+#############
+
+create_clock -period 3.333 -name sys_clk [get_pins u_ibufg_sys_clk/O]
+set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins u_ibufg_sys_clk/O]
+set_clock_groups -name sys_clk_async -asynchronous -group {sys_clk}
+
+#############
+# Mig clock #
+#############
+
+set MIG_RST [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst]
+create_clock -period 3.333 -name dram_axi_clk [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk]
+set_false_path -hold -through $MIG_RST
+set_max_delay -through $MIG_RST 3.333
+
+
+#################################################################################
+
+###############
+# ASSIGN PINS #
+###############
+
 #################################################
 ### ZCU102 Rev1.0 Master XDC file 09-15-2016 ####
 #################################################
@@ -155,8 +183,8 @@ set_property IOSTANDARD  LVCMOS33 [get_ports "uart_rx_i"] ;# Bank  49 VCCO - VCC
 #set_property IOSTANDARD  LVCMOS33 [get_ports "TRACEDATA4"] ;# Bank  48 VCCO - VCC3V3   - IO_L1N_AD15N_48
 #set_property PACKAGE_PIN H18      [get_ports "TRACEDATA3"] ;# Bank  48 VCCO - VCC3V3   - IO_L1P_AD15P_48
 #set_property IOSTANDARD  LVCMOS33 [get_ports "TRACEDATA3"] ;# Bank  48 VCCO - VCC3V3   - IO_L1P_AD15P_48
-set_property PACKAGE_PIN A20      [get_ports "jtag_tck_i"] ;# Bank  47 VCCO - VCC3V3   - IO_L12N_AD0N_47
-set_property IOSTANDARD  LVCMOS33 [get_ports "jtag_tck_i"] ;# Bank  47 VCCO - VCC3V3   - IO_L12N_AD0N_47
+set_property PACKAGE_PIN A20      [get_ports "jtag_tms_i"] ;# Bank  47 VCCO - VCC3V3   - IO_L12N_AD0N_47
+set_property IOSTANDARD  LVCMOS33 [get_ports "jtag_tms_i"] ;# Bank  47 VCCO - VCC3V3   - IO_L12N_AD0N_47
 set_property PACKAGE_PIN B20      [get_ports "jtag_tdi_i"] ;# Bank  47 VCCO - VCC3V3   - IO_L12P_AD0P_47
 set_property IOSTANDARD  LVCMOS33 [get_ports "jtag_tdi_i"] ;# Bank  47 VCCO - VCC3V3   - IO_L12P_AD0P_47
 set_property PACKAGE_PIN A22      [get_ports "jtag_tdo_o"] ;# Bank  47 VCCO - VCC3V3   - IO_L11N_AD1N_47
@@ -183,10 +211,10 @@ set_property IOSTANDARD  LVCMOS33 [get_ports "jtag_tck_i"] ;# Bank  47 VCCO - VC
 #set_property IOSTANDARD  LVCMOS33 [get_ports "PMOD1_4"] ;# Bank  47 VCCO - VCC3V3   - IO_L6N_HDGC_AD6N_47
 #set_property PACKAGE_PIN G20      [get_ports "PMOD1_5"] ;# Bank  47 VCCO - VCC3V3   - IO_L6P_HDGC_AD6P_47
 #set_property IOSTANDARD  LVCMOS33 [get_ports "PMOD1_5"] ;# Bank  47 VCCO - VCC3V3   - IO_L6P_HDGC_AD6P_47
-#set_property PACKAGE_PIN F21      [get_ports "CLK_125_N"] ;# Bank  47 VCCO - VCC3V3   - IO_L5N_HDGC_AD7N_47
-#set_property IOSTANDARD  LVDS_25  [get_ports "CLK_125_N"] ;# Bank  47 VCCO - VCC3V3   - IO_L5N_HDGC_AD7N_47
-#set_property PACKAGE_PIN G21      [get_ports "CLK_125_P"] ;# Bank  47 VCCO - VCC3V3   - IO_L5P_HDGC_AD7P_47
-#set_property IOSTANDARD  LVDS_25  [get_ports "CLK_125_P"] ;# Bank  47 VCCO - VCC3V3   - IO_L5P_HDGC_AD7P_47
+#set_property PACKAGE_PIN F21      [get_ports "sys_clk_n"] ;# Bank  47 VCCO - VCC3V3   - IO_L5N_HDGC_AD7N_47 -> CLK_125_N
+#set_property IOSTANDARD  LVDS_25  [get_ports "sys_clk_n"] ;# Bank  47 VCCO - VCC3V3   - IO_L5N_HDGC_AD7N_47 -> CLK_125_N
+#set_property PACKAGE_PIN G21      [get_ports "sys_clk_p"] ;# Bank  47 VCCO - VCC3V3   - IO_L5P_HDGC_AD7P_47 -> CLK_125_P
+#set_property IOSTANDARD  LVDS_25  [get_ports "sys_clk_p"] ;# Bank  47 VCCO - VCC3V3   - IO_L5P_HDGC_AD7P_47 -> CLK_125_P
 #set_property PACKAGE_PIN J20      [get_ports "PMOD1_6"] ;# Bank  47 VCCO - VCC3V3   - IO_L4N_AD8N_47
 #set_property IOSTANDARD  LVCMOS33 [get_ports "PMOD1_6"] ;# Bank  47 VCCO - VCC3V3   - IO_L4N_AD8N_47
 #set_property PACKAGE_PIN J19      [get_ports "PMOD1_7"] ;# Bank  47 VCCO - VCC3V3   - IO_L4P_AD8P_47
@@ -618,11 +646,11 @@ set_property IOSTANDARD  LVCMOS33 [get_ports "cpu_reset"] ;# Bank  44 VCCO - VCC
 #set_property IOSTANDARD  SSTL12_DCI [get_ports "DDR4_A15_CAS_B"] ;# Bank  64 VCCO - VCC1V2   - IO_L13N_T2L_N1_GC_QBC_64
 #set_property PACKAGE_PIN AL6      [get_ports "DDR4_DM0"] ;# Bank  64 VCCO - VCC1V2   - IO_L13P_T2L_N0_GC_QBC_64
 #set_property IOSTANDARD  POD12_DCI [get_ports "DDR4_DM0"] ;# Bank  64 VCCO - VCC1V2   - IO_L13P_T2L_N0_GC_QBC_64
-#set_property PACKAGE_PIN AL7      [get_ports "USER_SI570_N"] ;# Bank  64 VCCO - VCC1V2   - IO_L12N_T1U_N11_GC_64
-#set_property IOSTANDARD  DIFF_SSTL12 [get_ports "USER_SI570_N"] ;# Bank  64 VCCO - VCC1V2   - IO_L12N_T1U_N11_GC_64
-#set_property PACKAGE_PIN AL8      [get_ports "USER_SI570_P"] ;# Bank  64 VCCO - VCC1V2   - IO_L12P_T1U_N10_GC_64
-#set_property IOSTANDARD  DIFF_SSTL12 [get_ports "USER_SI570_P"] ;# Bank  64 VCCO - VCC1V2   - IO_L12P_T1U_N10_GC_64
-#set_property PACKAGE_PIN AK7      [get_ports "DDR4_BG0"] ;# Bank  64 VCCO - VCC1V2   - IO_L11N_T1U_N9_GC_64
+set_property PACKAGE_PIN AL7      [get_ports "sys_clk_n"] ;# Bank  64 VCCO - VCC1V2   - IO_L12N_T1U_N11_GC_64 => USER_SI570_N
+set_property IOSTANDARD  DIFF_SSTL12 [get_ports "sys_clk_n"] ;# Bank  64 VCCO - VCC1V2   - IO_L12N_T1U_N11_GC_64  => USER_SI570_N
+set_property PACKAGE_PIN AL8      [get_ports "sys_clk_p"] ;# Bank  64 VCCO - VCC1V2   - IO_L12P_T1U_N10_GC_64  => USER_SI570_P
+set_property IOSTANDARD  DIFF_SSTL12 [get_ports "sys_clk_p"] ;# Bank  64 VCCO - VCC1V2   - IO_L12P_T1U_N10_GC_64  => USER_SI570_P
+#set_property PACKAGE_PIN AK7      [get_ports "DDR4_BG0"] ;# Bank  64 VCCO - VCC1V2   - IO_L11N_T1U_N9_GC_64 
 #set_property IOSTANDARD  SSTL12_DCI [get_ports "DDR4_BG0"] ;# Bank  64 VCCO - VCC1V2   - IO_L11N_T1U_N9_GC_64
 #set_property PACKAGE_PIN AK8      [get_ports "DDR4_ACT_B"] ;# Bank  64 VCCO - VCC1V2   - IO_L11P_T1U_N8_GC_64
 #set_property IOSTANDARD  SSTL12_DCI [get_ports "DDR4_ACT_B"] ;# Bank  64 VCCO - VCC1V2   - IO_L11P_T1U_N8_GC_64

target/xilinx/scripts/flash.tcl

@@ -0,0 +1,50 @@
+# Copyright 2020 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+#
+# Nils Wistoff <[email protected]>
+# Noah Huetter <[email protected]>
+# 
+
+set mcs_file flash_img.mcs
+set file $::env(FILE)
+set offset $::env(OFFSET)
+
+# Create flash configuration file
+write_cfgmem -force -format mcs -size 256 -interface SPIx4 \
+  -loaddata "up $offset $file" \
+  -checksum \
+  -file $mcs_file
+
+# Open and connect HW manager
+open_hw_manager
+connect_hw_server -url $::env(HOST):$::env(PORT) -allow_non_jtag
+current_hw_target [get_hw_targets $::env(HOST):$::env(PORT)/$::env(FPGA_PATH)]
+set_property PARAM.FREQUENCY 15000000 [get_hw_targets $::env(HOST):$::env(PORT)/$::env(FPGA_PATH)]
+open_hw_target
+current_hw_device [get_hw_devices xcvu37p_0]
+
+# Add the SPI flash as configuration memory
+set hw_device [get_hw_devices xcvu37p_0]
+create_hw_cfgmem -hw_device $hw_device [lindex [get_cfgmem_parts {mt25qu02g-spi-x1_x2_x4}] 0]
+set hw_cfgmem [get_property PROGRAM.HW_CFGMEM $hw_device]
+set_property PROGRAM.ADDRESS_RANGE  {use_file} $hw_cfgmem
+set_property PROGRAM.FILES [list $mcs_file ] $hw_cfgmem
+set_property PROGRAM.PRM_FILE {} $hw_cfgmem
+set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} $hw_cfgmem
+set_property PROGRAM.BLANK_CHECK  0 $hw_cfgmem
+set_property PROGRAM.ERASE  0 $hw_cfgmem
+set_property PROGRAM.CFG_PROGRAM  1 $hw_cfgmem
+set_property PROGRAM.VERIFY  0 $hw_cfgmem
+set_property PROGRAM.CHECKSUM  0 $hw_cfgmem
+
+# Create bitstream to access SPI flash
+create_hw_bitstream -hw_device $hw_device [get_property PROGRAM.HW_CFGMEM_BITFILE $hw_device]; 
+program_hw_devices $hw_device; 
+refresh_hw_device $hw_device;
+
+# Program SPI flash
+program_hw_cfgmem -hw_cfgmem $hw_cfgmem
+
+# Close connection
+close_hw_manager

target/xilinx/scripts/run.tcl

@@ -16,27 +16,7 @@ switch $::env(BOARD) {
 }
 
 # Ips selection
-switch $::env(BOARD) {
-  "genesys2" - "kc705" - "vc707" {
-    set ips { "xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.xci" \
-              "xilinx/xlnx_vio/xlnx_vio.srcs/sources_1/ip/xlnx_vio/xlnx_vio.xci" \
-              "xilinx/xlnx_clk_wiz/xlnx_clk_wiz.srcs/sources_1/ip/xlnx_clk_wiz/xlnx_clk_wiz.xci"}
-  }
-  "vcu128" {
-    set ips { "xilinx/xlnx_mig_ddr4/xlnx_mig_ddr4.srcs/sources_1/ip/xlnx_mig_ddr4/xlnx_mig_ddr4.xci" \
-              "xilinx/xlnx_vio/xlnx_vio.srcs/sources_1/ip/xlnx_vio/xlnx_vio.xci" \
-              "xilinx/xlnx_clk_wiz/xlnx_clk_wiz.srcs/sources_1/ip/xlnx_clk_wiz/xlnx_clk_wiz.xci"}
-  }
-  "zcu102" {
-    set ips { "xilinx/xlnx_mig_ddr4/xlnx_mig_ddr4.srcs/sources_1/ip/xlnx_mig_ddr4/xlnx_mig_ddr4.xci" \
-              "xilinx/xlnx_vio/xlnx_vio.srcs/sources_1/ip/xlnx_vio/xlnx_vio.xci" \
-              "xilinx/xlnx_clk_wiz/xlnx_clk_wiz.srcs/sources_1/ip/xlnx_clk_wiz/xlnx_clk_wiz.xci"}
-  }
-  default {
-    set ips {}
-  }
-}
-
+set ips $::env(IP_PATHS)
 read_ip $ips
 
 source scripts/add_sources.tcl
@@ -72,6 +52,7 @@ report_clock_interaction                                                -file re
 # Instantiate ILA
 set DEBUG [llength [get_nets -hier -filter {MARK_DEBUG == 1}]]
 if ($DEBUG) {
+    remove_cell [get_cells -hier -filter {ORIG_REF_NAME == "unread" || REF_NAME == "unread"}]
     # Create core
     puts "Creating debug core..."
     create_debug_core u_ila_0 ila
@@ -120,11 +101,12 @@ launch_runs impl_1 -to_step write_bitstream
 wait_on_run impl_1
 
 # Check timing constraints
-open_run impl_1
 set timingrep [report_timing_summary -no_header -no_detailed_paths -return_string]
-if {! [string match -nocase {*timing constraints are met*} $timingrep]} {
-  send_msg_id {USER 1-1} ERROR {Timing constraints were not met.}
-  return -code error
+if {[info exists ::env(CHECK_TIMING)] && $::env(CHECK_TIMING)==1} {
+  if {! [string match -nocase {*timing constraints are met*} $timingrep]} {
+    send_msg_id {USER 1-1} ERROR {Timing constraints were not met.}
+    return -code error
+  }
 }
 
 # Output Verilog netlist + SDC for timing simulation