fpga: Testing ddr4

pulp-platform · Jul 17, 2023 · 0e9abf9 · 0e9abf9
1 parent e6dfb7f
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diff --git a/Bender.yml b/Bender.yml
@@ -47,7 +47,7 @@ sources:
       - target/sim/src/fixture_cheshire_soc.sv
       - target/sim/src/tb_cheshire_soc.sv
 
-  - target: all(fpga, xilinx)
+  - target: any(fpga, xilinx)
     files:
       - target/xilinx/src/fan_ctrl.sv
       - target/xilinx/src/dram_wrapper.sv

diff --git a/cheshire.mk b/cheshire.mk
@@ -55,7 +55,7 @@ chs-clean-deps:
 ######################
 
 CHS_NONFREE_REMOTE ?= [email protected]:pulp-restricted/cheshire-nonfree.git
-CHS_NONFREE_COMMIT ?= e702b4ce754c3b7c9a864a2ce8e2d2fa013056ea
+CHS_NONFREE_COMMIT ?= 65f089e9218084e872009cf1c557965914cacf05
 
 chs-nonfree-init:
 	git clone $(CHS_NONFREE_REMOTE) $(CHS_ROOT)/nonfree
@@ -158,3 +158,4 @@ chs-sim-all: $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl
 #############
 
 include $(CHS_ROOT)/target/xilinx/xilinx.mk
+include $(CHS_XIL_DIR)/sim/simulate.mk
diff --git a/target/xilinx/constraints/cheshire.xdc b/target/xilinx/constraints/cheshire.xdc
@@ -13,21 +13,12 @@
 set_property DONT_TOUCH TRUE [get_cells i_sys_clk_div/i_clk_bypass_mux]
 
 # The net of which we get the 200 MHz single ended clock from the MIG
-set MIG_CLK_SRC [get_pins -filter {DIRECTION == OUT} -leaf -of_objects [get_nets dram_clock_out]]
-set MIG_RST_SRC [get_pins -filter {DIRECTION == OUT} -leaf -of_objects [get_nets dram_sync_reset]]
-
 set SOC_RST_SRC [get_pins -filter {DIRECTION == OUT} -leaf -of_objects [get_nets rst_n]]
 
 #####################
 # Timing Parameters #
 #####################
 
-# 333 MHz (max) DRAM Axi clock
-set FPGA_TCK 3.0
-
-# 200 MHz DRAM Generated clock
-set DRAM_TCK 5.0
-
 # 50 MHz SoC clock
 set SOC_TCK 20.0
 
@@ -44,8 +35,15 @@ set UART_IO_SPEED 200.0
 # Clocks #
 ##########
 
+# Clk_wiz clocks
+create_clock -period 100 -name clk_10 [get_pins i_xlnx_clk_wiz/clk_10]
+create_clock -period 50 -name clk_20 [get_pins i_xlnx_clk_wiz/clk_20]
+create_clock -period 20 -name clk_50 [get_pins i_xlnx_clk_wiz/clk_50]
+create_clock -period 10 -name clk_100 [get_pins i_xlnx_clk_wiz/clk_100]
+
 # System Clock
-create_generated_clock -name clk_soc -source $MIG_CLK_SRC -divide_by 4 [get_nets soc_clk]
+# [see in board.xdc]
+
 # JTAG Clock
 create_clock -period $JTAG_TCK -name clk_jtag [get_ports jtag_tck_i]
 set_input_jitter clk_jtag 1.000
@@ -55,14 +53,7 @@ set_input_jitter clk_jtag 1.000
 ################
 
 # JTAG Clock is asynchronous to all other clocks
-set_clock_groups -name jtag_async -asynchronous -group [get_clocks clk_jtag]
-
-#######################
-# Placement Overrides #
-#######################
-
-# Accept suboptimal BUFG-BUFG cascades
-set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_sys_clk_div/i_clk_mux/clk0_i]
+set_clock_groups -name jtag_async -asynchronous -group {clk_jtag}
 
 ########
 # JTAG #
@@ -77,13 +68,6 @@ set_output_delay -max -clock clk_jtag [expr 0.20 * $JTAG_TCK] [get_ports jtag_td
 set_max_delay  -from [get_ports jtag_trst_ni] $JTAG_TCK
 set_false_path -hold -from [get_ports jtag_trst_ni]
 
-#######
-# MIG #
-#######
-
-set_max_delay  -from $MIG_RST_SRC $FPGA_TCK
-set_false_path -hold -from $MIG_RST_SRC
-
 ########
 # UART #
 ########
@@ -102,14 +86,4 @@ set_false_path -hold -to [get_ports uart_tx_o]
 set_property KEEP_HIERARCHY SOFT [get_cells i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*i_sync]
 set_false_path -hold -through [get_pins -of_objects [get_cells i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*]] -through [get_pins -of_objects [get_cells i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*]]
 set_max_delay -datapath -from [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_dst_*/*i_sync/reg*/D] $FPGA_TCK
-set_max_delay -datapath -from [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_src_*/*i_sync/reg*/D] $FPGA_TCK
 set_max_delay -datapath -from [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] $FPGA_TCK
-
-###################
-# Reset Generator #
-###################
-
-set_max_delay -from $SOC_RST_SRC $SOC_TCK
-set_false_path -hold -from $SOC_RST_SRC
-
-set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets i_xlnx_clk_wiz/inst/clkin1_ibufds/O]
diff --git a/target/xilinx/constraints/genesys2.xdc b/target/xilinx/constraints/genesys2.xdc
@@ -5,6 +5,24 @@
 # Testmode is set to 0 during normal use
 set_case_analysis 0 [get_ports testmode_i]
 
+#############
+# Sys clock #
+#############
+
+create_clock -period 5 -name sys_clk [get_pins u_ibufg_sys_clk/O]
+set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins u_ibufg_sys_clk/O]
+set_clock_groups -name sys_clk_async -asynchronous -group {sys_clk}
+
+
+#############
+# Mig clock #
+#############
+
+set MIG_RST [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst]
+create_clock -period 5 -name dram_axi_clk [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk]
+set_false_path -hold -through $MIG_RST
+set_max_delay -through $MIG_RST 5 
+
 #######
 # VGA #
 #######
@@ -54,8 +72,8 @@ set_false_path -hold -to [get_ports {i2c_scl_io i2c_sda_io}]
 ###############
 
 ## Clock Signal
-# set_property -dict { PACKAGE_PIN AD11  IOSTANDARD LVDS     } [get_ports { sysclk_n }]; #IO_L12N_T1_MRCC_33 Sch=sysclk_n
-# set_property -dict { PACKAGE_PIN AD12  IOSTANDARD LVDS     } [get_ports { sysclk_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p
+set_property -dict { PACKAGE_PIN AD11  IOSTANDARD LVDS     } [get_ports { sys_clk_n }]; #IO_L12N_T1_MRCC_33 Sch=sysclk_n
+set_property -dict { PACKAGE_PIN AD12  IOSTANDARD LVDS     } [get_ports { sys_clk_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p
 
 ## Buttons
 #set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS12 } [get_ports { btnc }]; #IO_25_17 Sch=btnc

diff --git a/target/xilinx/constraints/vcu128.xdc b/target/xilinx/constraints/vcu128.xdc
@@ -6,6 +6,27 @@
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_ports jtag_tck_i]]
 set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_ports jtag_tck_i]]
 
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_ports cpu_reset]]
+set_property CLOCK_BUFFER_TYPE NONE [get_nets -of [get_ports cpu_reset]]
+
+#############
+# Sys clock #
+#############
+
+create_clock -period 10 -name sys_clk [get_pins u_ibufg_sys_clk/O]
+set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins u_ibufg_sys_clk/O]
+set_clock_groups -name sys_clk_async -asynchronous -group {sys_clk}
+
+#############
+# Mig clock #
+#############
+
+set MIG_RST [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk_sync_rst]
+create_clock -period 10 -name dram_axi_clk [get_pins i_dram_wrapper/i_dram/c0_ddr4_ui_clk]
+set_false_path -hold -through $MIG_RST
+set_max_delay -through $MIG_RST 10
+
+
 #################################################################################
 
 ###############

diff --git a/target/xilinx/scripts/run.tcl b/target/xilinx/scripts/run.tcl
@@ -45,8 +45,8 @@ set_property top ${project}_top_xilinx [current_fileset]
 
 update_compile_order -fileset sources_1
 
-set_property strategy Flow_PerfOptimized_high [get_runs synth_1]
-set_property strategy Performance_ExtraTimingOpt [get_runs impl_1]
+set_property strategy Flow_RuntimeOptimized [get_runs synth_1]
+set_property strategy Flow_RuntimeOptimized [get_runs impl_1]
 
 set_property XPM_LIBRARIES XPM_MEMORY [current_project]
 

diff --git a/target/xilinx/sim/run_simulation.tcl b/target/xilinx/sim/run_simulation.tcl
@@ -6,8 +6,11 @@
 
 #source ips/xlnx_mig_7_ddr3_ex/questa/compile.do
 #source ips/xlnx_mig_7_ddr3/questa/compile.do
-source ips/xlnx_mig_ddr4_ex/questa/compile.do
-source ips/xlnx_mig_ddr4/questa/compile.do
+
+#source ips/xlnx_mig_ddr4_ex/questa/compile.do
+#source ips/xlnx_mig_ddr4/questa/compile.do
+#source ips/xlnx_clk_wiz/questa/compile.do
+#source ips/xlnx_vio/questa/compile.do
 source ../scripts/add_sources_vsim.tcl
 
 

diff --git a/target/xilinx/sim/simulate.mk b/target/xilinx/sim/simulate.mk
@@ -4,11 +4,13 @@
 #
 # Cyril Koenig <[email protected]>
 
+CHS_XIL_SIM_DIR  ?= $(CHS_XIL_DIR)/sim
+
 XILINX_SIMLIB_PATH ?= ~/xlib_questa-2022.3_vivado-2022.1
 SIMULATOR_PATH ?= /usr/pack/questa-2022.3-bt/questasim/bin
 GCC_PATH ?= /usr/pack/questa-2022.3-bt/questasim/gcc-7.4.0-linux_x86_64/bin
 
-ip-sim-scripts := $(addsuffix /questa/compile.do, $(addprefix sim/ips/, $(ips-names)))
+ip-sim-scripts := $(addsuffix /questa/compile.do, $(addprefix $(CHS_XIL_SIM_DIR)/ips/, $(ips-names)))
 
 # Pre-generated/modified example projects (contain the simulation top level)
 ifeq ($(BOARD),vcu128)
@@ -18,37 +20,37 @@ ifeq ($(BOARD),genesys2)
 	ip-example-projects := xlnx_mig_7_ddr3_ex
 endif
 
-ip-example-sim-scripts := $(addsuffix /questa/compile.do, $(addprefix sim/ips/, $(ip-example-projects)))
+ip-example-sim-scripts := $(addsuffix /questa/compile.do, $(addprefix $(CHS_XIL_SIM_DIR)/ips/, $(ip-example-projects)))
 
 VIVADOENV_SIM := $(VIVADOENV) \
               XILINX_SIMLIB_PATH=$(XILINX_SIMLIB_PATH) \
               SIMULATOR_PATH=$(SIMULATOR_PATH) \
 			  GCC_PATH=$(GCC_PATH) \
-			  VIVADO_PROJECT=../${PROJECT}.xpr
+			  VIVADO_PROJECT=$(CHS_XIL_DIR)/${PROJECT}.xpr
 VLOG_ARGS := -suppress 2583 -suppress 13314
 
 # Fetch example projects at IIS (containing SRAM behavioral models)
-sim/ips/%_ex/questa/compile.do:
-	tar -xvf /usr/scratch2/wuerzburg/cykoenig/export/$*_ex.tar -C sim/ips
+$(CHS_XIL_SIM_DIR)/ips/%_ex/questa/compile.do:
+	tar -xvf /usr/scratch2/wuerzburg/cykoenig/export/$*_ex.tar -C $(CHS_XIL_SIM_DIR)/ips
 
 # Generate simulation libraries
 $(XILINX_SIMLIB_PATH)/modelsim.ini:
-	cd sim && $(VIVADOENV_SIM) vitis-2022.1 vivado -nojournal -mode batch -source setup_simulation.tcl -tclargs "compile_simlib"
+	cd $(CHS_XIL_SIM_DIR) && $(VIVADOENV_SIM) vitis-2022.1 vivado -nojournal -mode batch -source setup_simulation.tcl -tclargs "compile_simlib"
 
 # 
-sim/ips/%/questa/compile.do:
-	cd sim && $(VIVADOENV_SIM) $(VIVADO) -nojournal -mode batch -source setup_simulation.tcl -tclargs "export_simulation"
+$(CHS_XIL_SIM_DIR)/ips/%/questa/compile.do:
+	cd $(CHS_XIL_SIM_DIR) && $(VIVADOENV_SIM) $(VIVADO) -nojournal -mode batch -source setup_simulation.tcl -tclargs "export_simulation"
 
-scripts/add_sources_vsim.tcl:
-	$(BENDER) script vsim -t sim -t test -t fpga -t cv64a6_imafdcsclic_sv39 -t cva6 $(bender-targets) --vlog-arg="$(VLOG_ARGS)" > $@
+$(CHS_XIL_DIR)/scripts/add_sources_vsim.tcl:
+	$(BENDER) script vsim -t sim -t test $(xilinx_targs) --vlog-arg="$(VLOG_ARGS)" > $@
 
-sim: ${PROJECT}.xpr $(XILINX_SIMLIB_PATH)/modelsim.ini $(ip-example-sim-scripts) $(ip-sim-scripts) scripts/add_sources_vsim.tcl
-	mkdir -p sim/questa_lib
-	cp $(XILINX_SIMLIB_PATH)/modelsim.ini sim
-	chmod +w sim/modelsim.ini
-	cd sim && questa-2022.3 vsim -work work -do "run_simulation.tcl"
+chs-xil-sim: $(CHS_XIL_DIR)/${PROJECT}.xpr $(XILINX_SIMLIB_PATH)/modelsim.ini $(ip-example-sim-scripts) $(ip-sim-scripts) $(CHS_XIL_DIR)/scripts/add_sources_vsim.tcl
+	mkdir -p $(CHS_XIL_SIM_DIR)/questa_lib
+	cp $(XILINX_SIMLIB_PATH)/modelsim.ini $(CHS_XIL_SIM_DIR)
+	chmod +w $(CHS_XIL_SIM_DIR)/modelsim.ini
+	cd $(CHS_XIL_SIM_DIR) && questa-2022.3 vsim -work work -do "run_simulation.tcl"
 
-clean-sim:
-	rm -rf sim/*.log sim/questa_lib sim/work sim/transcript sim/vsim.wlf scripts/vsim_cheshire.tcl sim/.Xil sim/modelsim.ini
+chs-xil-clean-sim:
+	cd $(CHS_XIL_DIR) && rm -rf sim/*.log sim/questa_lib sim/work sim/transcript sim/vsim.wlf scripts/vsim_cheshire.tcl sim/.Xil sim/modelsim.ini
 
 .PHONY: clean-sim sim
diff --git a/target/xilinx/src/cheshire_top_xilinx.sv b/target/xilinx/src/cheshire_top_xilinx.sv
@@ -203,6 +203,28 @@ module cheshire_top_xilinx
   (* dont_touch = "yes" *) wire soc_clk;
   (* dont_touch = "yes" *) wire rst_n;
 
+  ///////////////////
+  // GPIOs         // 
+  ///////////////////
+
+  // Tie off signals if no switches on the board
+`ifndef USE_SWITCHES
+  logic         testmode_i;
+  logic [1:0]   boot_mode_i;
+  assign testmode_i  = '0;
+  assign boot_mode_i = 2'b00;
+`endif
+
+  // Give VDD and GND to JTAG dongle
+`ifdef USE_JTAG_VDDGND
+  assign jtag_vdd_o  = '1;
+  assign jtag_gnd_o  = '0;
+`endif
+`ifndef USE_JTAG_TRSTN
+  logic jtag_trst_ni;
+  assign jtag_trst_ni = '1;
+`endif
+
   //////////////////
   // Clock Wizard //
   //////////////////
@@ -239,7 +261,7 @@ module cheshire_top_xilinx
   rstgen i_rstgen_main (
     .clk_i        ( soc_clk                  ),
     .rst_ni       ( ~sys_rst                 ),
-    .test_mode_i  ( test_mode_i              ),
+    .test_mode_i  ( testmode_i              ),
     .rst_no       ( rst_n                    ),
     .init_no      (                          ) // keep open
   );
@@ -251,36 +273,21 @@ module cheshire_top_xilinx
   logic       vio_reset, vio_boot_mode_sel;
   logic [1:0] vio_boot_mode;
 
+`ifdef USE_VIO
   xlnx_vio i_xlnx_vio (
     .clk(soc_clk),
     .probe_out0(vio_reset),
     .probe_out1(vio_boot_mode),
     .probe_out2(vio_boot_mode_sel)
   );
-  assign sys_rst = ~cpu_resetn | vio_reset;
-  assign boot_mode = vio_boot_mode_sel ? vio_boot_mode : boot_mode_i;
-
-  ///////////////////
-  // GPIOs         // 
-  ///////////////////
-
-  // Tie off signals if no switches on the board
-`ifndef USE_SWITCHES
-  logic         testmode_i;
-  logic [1:0]   boot_mode_i;
-  assign testmode_i  = '0;
-  assign boot_mode_i = 2'b00;
+`else
+  assign vio_reset = '0;
+  assign vio_boot_mode = '0;
+  assign vio_boot_mode_sel = '0;
 `endif
 
-  // Give VDD and GND to JTAG dongle
-`ifdef USE_JTAG_VDDGND
-  assign jtag_vdd_o  = '1;
-  assign jtag_gnd_o  = '0;
-`endif
-`ifndef USE_JTAG_TRSTN
-  logic jtag_trst_ni;
-  assign jtag_trst_ni = '1;
-`endif
+  assign sys_rst = ~cpu_resetn | vio_reset;
+  assign boot_mode = vio_boot_mode_sel ? vio_boot_mode : boot_mode_i;
 
   //////////////
   // DRAM MIG //
@@ -289,12 +296,12 @@ module cheshire_top_xilinx
 `ifdef USE_DDR
   dram_wrapper #(
     .axi_soc_aw_chan_t ( axi_llc_aw_chan_t ),
-    .axi_soc_w_chan_t  ( axi_llc_w_chan_t ),
-    .axi_soc_b_chan_t  ( axi_llc_b_chan_t ),
+    .axi_soc_w_chan_t  ( axi_llc_w_chan_t  ),
+    .axi_soc_b_chan_t  ( axi_llc_b_chan_t  ),
     .axi_soc_ar_chan_t ( axi_llc_ar_chan_t ),
-    .axi_soc_r_chan_t  ( axi_llc_r_chan_t ),
-    .axi_soc_req_t     (axi_llc_req_t),
-    .axi_soc_resp_t    (axi_llc_rsp_t)
+    .axi_soc_r_chan_t  ( axi_llc_r_chan_t  ),
+    .axi_soc_req_t     ( axi_llc_req_t     ),
+    .axi_soc_resp_t    ( axi_llc_rsp_t     )
   ) i_dram_wrapper (
     // Rst
     .sys_rst_i                  ( sys_rst   ),
@@ -400,7 +407,7 @@ module cheshire_top_xilinx
   logic [3:0]           qspi_dqo_ts;
   logic [3:0]           qspi_dqo;
   logic [SpihNumCs-1:0] qspi_cs_b;
-logic [SpihNumCs-1:0] qspi_cs_b_ts;
+  logic [SpihNumCs-1:0] qspi_cs_b_ts;
 
   assign qspi_clk      = spi_sck_soc;
   assign qspi_cs_b     = spi_cs_soc;
@@ -472,7 +479,6 @@ logic [SpihNumCs-1:0] qspi_cs_b_ts;
     end
   end
 
-
   /////////////////
   // Fan Control //
   /////////////////
@@ -503,7 +509,6 @@ logic [SpihNumCs-1:0] qspi_cs_b_ts;
     .rsp_o ( ext_rsp  )
   );
 
-
   //////////////////
   // Cheshire SoC //
   //////////////////