fpga: Moved to flavoured flow

Bender.yml

@@ -50,9 +50,14 @@ sources:
       - target/sim/src/fixture_cheshire_soc.sv
       - target/sim/src/tb_cheshire_soc.sv
 
-  - target: all(fpga, xilinx)
+  - target: all(fpga, xilinx, xilinx_vanilla)
     files:
-      - target/xilinx/src/fan_ctrl.sv
-      - target/xilinx/src/dram_wrapper_xilinx.sv
-      - target/xilinx/src/phy_definitions.svh
-      - target/xilinx/src/cheshire_top_xilinx.sv
+      - target/xilinx/flavor_vanilla/src/fan_ctrl.sv
+      - target/xilinx/flavor_vanilla/src/dram_wrapper_xilinx.sv
+      - target/xilinx/flavor_vanilla/src/phy_definitions.svh
+      - target/xilinx/flavor_vanilla/src/cheshire_top_xilinx.sv
+
+  - target: all(fpga, xilinx, xilinx_bd)
+    files:
+      - target/xilinx/flavor_bd/src/cheshire_ip_wrapper.v
+      - target/xilinx/flavor_bd/src/cheshire_top_xilinx.sv

cheshire.mk

@@ -11,9 +11,6 @@ BENDER ?= bender
 VLOG_ARGS ?= -suppress 2583 -suppress 13314
 VSIM      ?= vsim
 
-# Define board for FPGA flow and/or device tree selection
-BOARD         ?= genesys2
-
 # Define used paths (prefixed to avoid name conflicts)
 CHS_ROOT      ?= $(shell $(BENDER) path cheshire)
 CHS_REG_DIR   := $(shell $(BENDER) path register_interface)
@@ -56,7 +53,7 @@ chs-clean-deps:
 ######################
 
 CHS_NONFREE_REMOTE ?= [email protected]:pulp-restricted/cheshire-nonfree.git
-CHS_NONFREE_COMMIT ?= 890a09d20bf200c4fbcc3d2b708a16ba89678306
+CHS_NONFREE_COMMIT ?= d31389c3b559e48496b7264a55ae33eda994bded
 
 chs-nonfree-init:
 	git clone $(CHS_NONFREE_REMOTE) $(CHS_ROOT)/nonfree
@@ -162,9 +159,6 @@ CHS_SIM_ALL += $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl
 #############
 
 include $(CHS_ROOT)/target/xilinx/xilinx.mk
-include $(CHS_XIL_DIR)/sim/sim.mk
-CHS_XILINX_ALL += $(CHS_XIL_DIR)/scripts/add_sources.tcl
-CHS_LINUX_IMG  += $(CHS_SW_DIR)/boot/linux-${BOARD}.gpt.bin
 
 #################################
 # Phonies (KEEP AT END OF FILE) #
@@ -179,5 +173,3 @@ chs-sw-all:      $(CHS_SW_ALL)
 chs-hw-all:      $(CHS_HW_ALL)
 chs-bootrom-all: $(CHS_BOOTROM_ALL)
 chs-sim-all:     $(CHS_SIM_ALL)
-chs-xilinx-all:  $(CHS_XILINX_ALL)
-chs-linux-img:   $(CHS_LINUX_IMG)

sw/boot/cheshire_vcu128_vanilla.dts

@@ -0,0 +1,27 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Cyril Koenig <[email protected]>
+
+/include/ "cheshire.dtsi"
+
+&spi {
+  boot-with = <1>;
+  nor@1 {
+    #address-cells = <0x1>;
+    #size-cells = <0x1>;
+    // Note : u-boot does not find mt25qu02g
+    compatible = "mt25qu02g", "jedec,spi-nor";
+    reg = <0x1>; // CS
+    spi-max-frequency = <25000000>;
+    spi-rx-bus-width = <0x1>;
+    spi-tx-bus-width = <0x1>;
+    disable-wp;
+    partition@0 {
+      label = "all";
+      reg = <0x0 0x6000000>; // 96 MB
+      read-only;
+    };
+  };
+};

target/xilinx/flavor_bd/constraints/ooc_cheshire_ip.xdc

@@ -0,0 +1,5 @@
+create_clock -name carfield_ooc_synth_clk_100 -period 100 [get_ports clk_100]
+create_clock -name carfield_ooc_synth_clk_50 -period 50 [get_ports clk_50]
+create_clock -name carfield_ooc_synth_clk_20 -period 20 [get_ports clk_20]
+create_clock -name carfield_ooc_synth_clk_10 -period 10 [get_ports clk_10]
+set_case_analysis 0 [get_ports testmode_i]

target/xilinx/flavor_bd/constraints/vcu128.xdc

@@ -0,0 +1,30 @@
+# VIOs are asynchronous
+set_false_path -through [get_pins -of_objects [get_cells design_1_i/vio_0] -filter {NAME =~ *probe*}]
+
+# Create system clocks
+create_clock -period 10 -name sys_clk [get_pins design_1_i/util_ds_buf_0/IBUF_OUT]
+set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins design_1_i/util_ds_buf_0/IBUF_OUT]
+create_clock -period 10 -name pcie_clk [get_nets design_1_i/util_ds_buf_1/U0/IBUF_OUT[0]]
+create_clock -period 10 -name pcie_clk_div [get_nets design_1_i/util_ds_buf_1/U0/IBUF_DS_ODIV2[0]]
+set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets design_1_i/util_ds_buf_1/U0/IBUF_DS_ODIV2[0]]
+set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets design_1_i/util_ds_buf_1/U0/IBUF_OUT[0]]
+
+# Pin related
+
+set_property LOC [get_package_pins -of_objects [get_bels [get_sites -filter {NAME =~ *COMMON*} -of_objects [get_iobanks -of_objects [get_sites GTYE4_CHANNEL_X1Y15]]]/REFCLK0P]] [get_ports pcie_refclk_clk_p[0]]
+set_property LOC [get_package_pins -of_objects [get_bels [get_sites -filter {NAME =~ *COMMON*} -of_objects [get_iobanks -of_objects [get_sites GTYE4_CHANNEL_X1Y15]]]/REFCLK0N]] [get_ports pcie_refclk_clk_n[0]]
+
+set_property PACKAGE_PIN BP26     [get_ports "uart_rx_i"] ;# Bank  67 VCCO - VCC1V8   - IO_L2N_T0L_N3_67
+set_property IOSTANDARD  LVCMOS18 [get_ports "uart_rx_i"] ;# Bank  67 VCCO - VCC1V8   - IO_L2N_T0L_N3_67
+set_property PACKAGE_PIN BN26     [get_ports "uart_tx_o"] ;# Bank  67 VCCO - VCC1V8   - IO_L2P_T0L_N2_67
+set_property IOSTANDARD  LVCMOS18 [get_ports "uart_tx_o"] ;# Bank  67 VCCO - VCC1V8   - IO_L2P_T0L_N2_67
+
+set_property PACKAGE_PIN BM29 [get_ports cpu_reset]
+set_property IOSTANDARD LVCMOS12 [get_ports cpu_reset]
+
+set_property BOARD_PART_PIN default_100mhz_clk_n [get_ports sys_clk_clk_n[0]]
+set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_clk_n[0]]
+set_property BOARD_PART_PIN default_100mhz_clk_p [get_ports sys_clk_clk_p[0]]
+set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_clk_p[0]]
+set_property PACKAGE_PIN BH51 [get_ports sys_clk_clk_p[0]]
+set_property PACKAGE_PIN BJ51 [get_ports sys_clk_clk_n[0]]

target/xilinx/flavor_bd/constraints/vcu128_ext_jtag.xdc

@@ -0,0 +1,17 @@
+set_property PACKAGE_PIN A23     [get_ports jtag_gnd_o] ;# A23 - C15 (FMCP_HSPC_LA10_N) - J1.04 - GND
+set_property IOSTANDARD LVCMOS18 [get_ports jtag_gnd_o] ;
+
+set_property PACKAGE_PIN B23     [get_ports jtag_vdd_o] ;# B23 - C14 (FMCP_HSPC_LA10_P) - J1.02 - VDD
+set_property IOSTANDARD LVCMOS18 [get_ports jtag_vdd_o] ;
+
+set_property PACKAGE_PIN B25     [get_ports jtag_tdo_o] ;# B25 - H17 (FMCP_HSPC_LA11_N) - J1.08 - TDO
+set_property IOSTANDARD LVCMOS18 [get_ports jtag_tdo_o]
+
+set_property PACKAGE_PIN B26     [get_ports jtag_tck_i] ;# B26 - H16 (FMCP_HSPC_LA11_P) - J1.06 - TCK
+set_property IOSTANDARD LVCMOS18 [get_ports jtag_tck_i] ;
+
+set_property PACKAGE_PIN H22     [get_ports jtag_tms_i] ;# H22 - G16 (FMCP_HSPC_LA12_N) - J1.12 - TNS
+set_property IOSTANDARD LVCMOS18 [get_ports jtag_tms_i] ;
+
+set_property PACKAGE_PIN J22     [get_ports jtag_tdi_i] ;# J22 - G15 (FMCP_HSPC_LA12_P) - J1.10 - TDI
+set_property IOSTANDARD LVCMOS18 [get_ports jtag_tdi_i]

target/xilinx/flavor_bd/flavor_bd.mk

@@ -0,0 +1,50 @@
+# Copyright 2022 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Cyril Koenig <[email protected]>
+
+# Output bitstream
+xilinx_bit_bd = $(CHS_XIL_DIR)/flavor_bd/out/design_1_wrapper.bit
+
+# Vivado variables
+vivado_env_bd := \
+    XILINX_PROJECT=$(XILINX_PROJECT) \
+    XILINX_BOARD=$(XILINX_BOARD) \
+    XILINX_PART=$(xilinx_part) \
+    XILINX_BOARD_LONG=$(xilinx_board_long) \
+    XILINX_PORT=$(XILINX_PORT) \
+    XILINX_HOST=$(XILINX_HOST) \
+    XILINX_FPGA_PATH=$(XILINX_FPGA_PATH) \
+    XILINX_BIT=$(xilinx_bit) \
+    GEN_NO_HYPERBUS=$(GEN_NO_HYPERBUS) \
+    GEN_EXT_JTAG=$(GEN_EXT_JTAG) \
+    XILINX_ROUTED_DCP=$(XILINX_ROUTED_DCP) \
+    XILINX_CHECK_TIMING=$(XILINX_CHECK_TIMING) \
+    XILINX_ELABORATION_ONLY=$(XILINX_ELABORATION_ONLY)
+
+# Flavor specific bender args
+xilinx_targs_bd := -t xilinx_bd
+
+# Add source files for ip
+$(CHS_XIL_DIR)/flavor_bd/scripts/add_sources_cheshire_ip.tcl: Bender.yml
+	$(BENDER) script vivado $(xilinx_targs) $(xilinx_targs_bd) > $@
+
+# Build Cheshire IP
+$(CHS_XIL_DIR)/flavor_bd/cheshire_ip/cheshire_ip.xpr: $(CHS_XIL_DIR)/flavor_bd/scripts/add_sources_cheshire_ip.tcl
+	cd $(CHS_XIL_DIR)/flavor_bd && $(vivado_env) $(VIVADO) $(VIVADO_FLAGS) -source scripts/run_cheshire_ip.tcl
+
+# Add includes files for block design
+$(CHS_XIL_DIR)/flavor_bd/scripts/add_includes.tcl:
+	$(BENDER) script vivado --only-defines --only-includes $(xilinx_targs) $(xilinx_targs_bd) > $@
+
+# Build block design bitstream
+$(CHS_XIL_DIR)/flavor_bd/out/%.bit: $(CHS_XIL_DIR)/flavor_bd/scripts/add_includes.tcl $(CHS_XIL_DIR)/flavor_bd/cheshire_ip/cheshire_ip.xpr
+	mkdir -p $(CHS_XIL_DIR)/flavor_bd/out
+	cd $(CHS_XIL_DIR)/flavor_bd && $(vivado_env_bd) $(VIVADO) $(VIVADO_FLAGS) -source scripts/run.tcl
+	find $(CHS_XIL_DIR)/flavor_bd -name "*.ltx" -o -name "*.bit" -o -name "*routed.rpt" | xargs -I {} cp {} $(CHS_XIL_DIR)/flavor_bd/out
+
+chs-xil-clean-bd:
+	cd $(CHS_XIL_DIR)/flavor_bd && rm -rf scripts/add_sources* scripts/add_includes* *.log *.jou *.str *.mif cheshire* .Xil/
+
+.PHONY: chs-xil-clean-bd

target/xilinx/flavor_bd/scripts/cheshire_bd_ext_jtag.tcl

@@ -0,0 +1,18 @@
+# Copyright 2020 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+#
+# Cyril Koenig <[email protected]>
+
+set jtag_gnd_o [ create_bd_port -dir O jtag_gnd_o ]
+set jtag_tck_i [ create_bd_port -dir I jtag_tck_i ]
+set jtag_tdi_i [ create_bd_port -dir I jtag_tdi_i ]
+set jtag_tdo_o [ create_bd_port -dir O jtag_tdo_o ]
+set jtag_tms_i [ create_bd_port -dir I jtag_tms_i ]
+set jtag_vdd_o [ create_bd_port -dir O jtag_vdd_o ]
+connect_bd_net -net cheshire_xilinx_ip_0_jtag_gnd_o [get_bd_ports jtag_gnd_o] [get_bd_pins cheshire_xilinx_ip_0/jtag_gnd_o]
+connect_bd_net -net cheshire_xilinx_ip_0_jtag_tdo_o [get_bd_ports jtag_tdo_o] [get_bd_pins cheshire_xilinx_ip_0/jtag_tdo_o]
+connect_bd_net -net cheshire_xilinx_ip_0_jtag_vdd_o [get_bd_ports jtag_vdd_o] [get_bd_pins cheshire_xilinx_ip_0/jtag_vdd_o]
+connect_bd_net -net jtag_tck_i_1 [get_bd_ports jtag_tck_i] [get_bd_pins cheshire_xilinx_ip_0/jtag_tck_i]
+connect_bd_net -net jtag_tdi_i_1 [get_bd_ports jtag_tdi_i] [get_bd_pins cheshire_xilinx_ip_0/jtag_tdi_i]
+connect_bd_net -net jtag_tms_i_1 [get_bd_ports jtag_tms_i] [get_bd_pins cheshire_xilinx_ip_0/jtag_tms_i]