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fpga: Add VCU128 flow and other IPs #1354

fpga: Add VCU128 flow and other IPs

fpga: Add VCU128 flow and other IPs #1354

Workflow file for this run

# Copyright 2022 ETH Zurich and University of Bologna.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
# Author: Paul Scheffler <[email protected]>
name: lint
on: [ push, pull_request, workflow_dispatch ]
jobs:
lint-license:
runs-on: ubuntu-latest
steps:
-
name: Checkout
uses: actions/checkout@v3
-
name: Check license
uses: pulp-platform/pulp-actions/lint-license@v2
with:
license: |
Copyright (\d{4}(-\d{4})?\s)?(ETH Zurich and University of Bologna|lowRISC contributors).
(Solderpad Hardware License, Version 0.51|Licensed under the Apache License, Version 2.0), see LICENSE for details.
SPDX-License-Identifier: (SHL-0.51|Apache-2.0)
# Exclude generated headers (no license checker support for optional lines)
exclude_paths: |
sw/include/regs/*.h
lint-sv:
runs-on: ubuntu-latest
steps:
-
name: Checkout
uses: actions/checkout@v3
-
name: Run Verible
uses: chipsalliance/verible-linter-action@main
with:
paths: hw
extra_args: "--waiver_files .github/verible.waiver"
github_token: ${{ secrets.GITHUB_TOKEN }}
fail_on_error: true
reviewdog_reporter: github-check
lint-cxx:
runs-on: ubuntu-latest
steps:
-
name: Checkout
uses: actions/checkout@v3
-
name: Run Clang-format
uses: DoozyX/[email protected]
with:
extensions: 'c,h,cpp'
clangFormatVersion: 14
style: >
{
IndentWidth: 4,
ColumnLimit: 100,
AlignEscapedNewlines: DontAlign,
SortIncludes: false,
AllowShortFunctionsOnASingleLine: None,
AllowShortIfStatementsOnASingleLine: true,
AllowShortLoopsOnASingleLine: true
}
exclude: |
./sw/include/regs/*.h
./target/sim/src/elfloader.cpp