Merge pull request #8 from pulp-platform/aottaviano/cva6-clic

Wire interrupts in Carfield

Bender.lock

@@ -126,7 +126,7 @@ packages:
     - register_interface
     - tech_cells_generic
   cheshire:
-    revision: 9f0234c1a40cd332f2b502cbbb5f98bd242b29ba
+    revision: 3b773c80985294375421c8f8ad57c009c74b3d46
     version: null
     source:
       Git: https://github.com/pulp-platform/cheshire.git
@@ -136,11 +136,13 @@ packages:
     - axi_llc
     - axi_riscv_atomics
     - axi_vga
+    - clic
     - clint
     - common_cells
     - common_verification
     - cva6
     - idma
+    - irq_router
     - opentitan_peripherals
     - register_interface
     - riscv-dbg
@@ -149,7 +151,7 @@ packages:
     revision: bed98f88761ca86706c36c4c33ac600d88c42373
     version: null
     source:
-      Git: https://github.com/pulp-platform/clic.git
+      Git: https://github.com/pulp-platform/clic
     dependencies:
     - common_cells
     - register_interface
@@ -306,6 +308,15 @@ packages:
     - common_cells
     - common_verification
     - register_interface
+  irq_router:
+    revision: d1d31350b24f3965b3a51e1bc96c71eb34e94db3
+    version: null
+    source:
+      Git: https://github.com/pulp-platform/irq_router
+    dependencies:
+    - axi
+    - common_cells
+    - register_interface
   l2_tcdm_hybrid_interco:
     revision: fa55e72859dcfb117a2788a77352193bef94ff2b
     version: 1.0.0

Bender.yml

@@ -12,7 +12,7 @@ package:
 dependencies:
   register_interface: { git: https://github.com/pulp-platform/register_interface.git,   rev: 2bb08879bc2ceabe2b6a0dc283753048a739e27b } # branch: main until newer version tag later than v0.4.0
   axi:                { git: https://github.com/pulp-platform/axi.git,                  version: 0.39.0-beta.9                        } # overridden in Bender.local to use axi-rt feature
-  cheshire:           { git: https://github.com/pulp-platform/cheshire.git,             rev: 9f0234c1a40cd332f2b502cbbb5f98bd242b29ba } # branch: main
+  cheshire:           { git: https://github.com/pulp-platform/cheshire.git,             rev: 3b773c80985294375421c8f8ad57c009c74b3d46 } # branch: aottaviano/cva6-clic
   hyperbus:           { git: https://github.com/pulp-platform/hyperbus.git,             rev: 2adb7271438cdb96c19fbaf3e2a6bf89ffeee568 } # branch: lv/phys_in_use
   car_l2:             { git: [email protected]:carfield/carfield_l2_mem.git,       rev: 08503a05307ef556ed5439619c70c039ff93d77a } # branch: main
   safety_island:      { git: [email protected]:carfield/safety-island.git,         rev: 60e768a3ef29f47339e31674d497293f5a768893 } # branch: atops

carfield.mk

@@ -17,6 +17,13 @@ TBENCH   ?= tb_carfield_soc
 BOOTMODE ?= 0 # default passive bootmode
 PRELMODE ?= 1 # default serial link preload
 VOPTARGS ?=
+# Interrupt configuration in cheshire
+# CLINT interruptible harts
+CLINTCORES     := 3
+# PLIC interruptible harts
+PLICCORES      := 6
+# PLIC number of input interrupts
+PLIC_NUM_INTRS := 128
 
 # Include cheshire's makefrag only if the dependency was cloned
 -include $(CHS_ROOT)/cheshire.mk
@@ -100,6 +107,18 @@ hw/regs/carfield_reg_pkg.sv hw/regs/carfield_reg_top.sv: hw/regs/carfield_regs.h
 ## not forget to check in the generated RTL.
 regenerate_soc_regs: hw/regs/carfield_reg_pkg.sv hw/regs/carfield_reg_top.sv
 
+## @section Carfield CLINT and PLIC interruptible harts configuration
+
+## The default configuration in cheshire allows for one interruptible hart. When the number of
+## external interruptible harts is updated in the cheshire cfg (cheshire_pkg.sv), we need to
+## regenerate the PLIC and CLINT accordingly.
+## CLINT: define CLINTCORES used in cheshire.mk before including the makefrag.
+## PLIC: edit the hjson configuration file in cheshire.
+.PHONY: update_plic
+update_plic: $(CHS_ROOT)/hw/rv_plic.cfg.hjson
+	sed -i 's/src: .*/src: $(PLIC_NUM_INTRS),/' $<
+	sed -i 's/target: .*/target: $(PLICCORES),/' $<
+
 $(CAR_ROOT)/tb/hyp_vip:
 	rm -rf $@
 	mkdir $@
@@ -164,30 +183,41 @@ car-checkout-deps:
 .PHONY: car-checkout
 car-checkout: car-checkout-deps
 
+## @section Carfield initialization
 .PHONY: car-hw-init
+## Initialize carfield by generating cheshire and spatz registers and wrapper, respectively
+## This step takes care of the generation of the missing hardware, or an update of the configuration
+## of some IPs, such as the PLIC or CLINT.
 car-hw-init: spatz-hw-init chs-hw-init
 
 .PHONY: spatz-hw-init
 spatz-hw-init:
 	$(MAKE) -C $(SPATZ_MAKEDIR) -B SPATZ_CLUSTER_CFG=carfield.hjson bootrom
 
 .PHONY: chs-hw-init
-chs-hw-init:
+## This target has a prerequisite, i.e. the PLIC configuration must be chosen before generating the
+## hardware.
+chs-hw-init: update_plic
 	$(MAKE) chs-hw-all
 
 .PHONY: chs-sim-init
+## Downloads verification IPs for SPI and I2C from cheshire and used by Carfield.
 chs-sim-init:
 	$(MAKE) chs-sim-all
 
 .PHONY: chs-sw-build
+## Builds the SW libraries in cheshire and generates an archive (`libcheshire.a`) available for
+## carfield as static library at link time.
 chs-sw-build:
 	$(MAKE) chs-sw-all
 
 .PHONY: car-sw-build
+## Builds carfield application SW and specific libraries. It links against `libcheshire.a`.
 car-sw-build: chs-sw-build
 	$(MAKE) car-sw-all
 
 .PHONY: car-init
+## Shortcut to initialize carfield with all the targets described above.
 car-init: car-checkout car-hw-init car-sim-init car-sw-build
 
 ############